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Bus controller and information processing device providing reduced idle cycle time during synchronization

  • US 5,916,311 A
  • Filed: 03/20/1997
  • Issued: 06/29/1999
  • Est. Priority Date: 03/27/1996
  • Status: Expired due to Term
First Claim
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1. A bus controller for controlling an access to a bus connected to a first device which operates in synchronization with a first clock signal and a second device which operates in asynchronization with the first clock signal, the controller comprising:

  • a detector for receiving an access request from a central processing unit which operates in synchronization with a second clock signal different from the first clock signal and for detecting whether the access request represents an access to the first device or an access to the second device, the detector including a synchronous clock data storage section having synchronous clock data stored therein indicative of whether an access controlling signal is to be generated in synchronization with the first clock signal or the second clock signal; and

    an access controlling signal generator, responsive to the detector, for generating a first access controlling signal for controlling an access of the first device to the bus in synchronization with the first clock signal and for supplying the first access controlling signal to the first device in a case where the access request represents the access to the first device, the access controlling signal generator generating a second access controlling signal for controlling an access of the second device to the bus in synchronization with the second clock signal and for supplying the second access controlling signal to the second device in a case where the access request represents the access to the second device.

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