Bus controller and information processing device providing reduced idle cycle time during synchronization

• US 5,916,311 A
• Filed: 03/20/1997
• Issued: 06/29/1999
• Est. Priority Date: 03/27/1996
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kakiage, Touru
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US08/821,596
• Time in Patent Office: 831 Days
• Field of Search: 395/284-287, 395/306-311, 395/551, 395/553, 395/556, 395/836, 395/892, 395/881, 395/882, 395/800.29-800.31, 395/800.43, 711/167
• US Class Current: 710/107
• CPC Class Codes: G06F 13/423 with synchronous protocol

Abstract

A bus controller controls an access to a bus connected to a first device which operates in synchronization with a first clock signal and a second device which operates in asynchronization with the first clock signal. The controller includes a detector. The detector receives an access request from a central processing unit which operates in synchronization with a second clock signal different from the first clock signal to detect whether the access request represents an access to the first device or an access to the second device. The controller further includes an access controlling signal generator. The access controlling signal generator generates a first access controlling signal for controlling an access of the first device to the bus in synchronization with the first clock signal and for supplying the first access controlling signal to the first device, in a case where the access request represents the access to the first device. The access controlling signal generator generates a second access controlling signal for controlling an access of the second device to the bus in synchronization with the second clock signal and for supplying the second access controlling signal to the second device, in a case where the access request represents the access to the second device.

Claims

1. A bus controller for controlling an access to a bus connected to a first device which operates in synchronization with a first clock signal and a second device which operates in asynchronization with the first clock signal, the controller comprising:

a detector for receiving an access request from a central processing unit which operates in synchronization with a second clock signal different from the first clock signal and for detecting whether the access request represents an access to the first device or an access to the second device, the detector including a synchronous clock data storage section having synchronous clock data stored therein indicative of whether an access controlling signal is to be generated in synchronization with the first clock signal or the second clock signal; and

an access controlling signal generator, responsive to the detector, for generating a first access controlling signal for controlling an access of the first device to the bus in synchronization with the first clock signal and for supplying the first access controlling signal to the first device in a case where the access request represents the access to the first device, the access controlling signal generator generating a second access controlling signal for controlling an access of the second device to the bus in synchronization with the second clock signal and for supplying the second access controlling signal to the second device in a case where the access request represents the access to the second device.

2. A bus controller according to claim 1, wherein a frequency of the second clock signal is higher than a frequency of the first clock signal.

3. A bus controller according to claim 1, wherein the access request includes at least a part of an address which defines a position to be accessed in the first device and the second device.

4. A bus controller according to claim 1, wherein the synchronous clock data storage section stores a plurality of synchronous clock data, each of the plurality of synchronous clock data determining whether an access to a corresponding address space among a plurality of address spaces is performed in synchronization with the first clock signal or the second clock signal;

and

a selector for selecting one of the plurality of synchronous clock data stored in the synchronous clock data storage section in accordance with an identifying signal for identifying one of the plurality of address spaces.

5. A bus controller according to claim 1, wherein the access controlling signal generator comprises:

a selector for selecting one of the first clock signal and the second clock signal based on a detection result of the detector; and

a generator for generating one of the first access controlling signal and the second access controlling signal based on an output from the selector.

6. A bus controller according to claim 1, further comprising a wait controller for generating a bus cycle ending signal for indicating an end of a bus cycle in synchronization with the second clock signal, and outputting the bus cycle ending signal to the access controlling signal generator.

7. A bus controller according to claim 6, wherein the wait controller comprises:

a wait cycle data storage section for storing a plurality of wait cycle data, each of the plurality of wait cycle data representing a wait cycle number with respect to a corresponding address space among a plurality of address spaces in a cycle unit of the second clock signal;

a selector for selecting one of the plurality of wait cycle data stored in the wait cycle data storage section in accordance with an identifying signal for identifying one of the plurality of address spaces; and

a counter for counting a bus cycle number in a cycle unit of the second clock signal based on an output from the selector, and outputting the bus cycle ending signal in a case where the bus cycle number reaches a predetermined value.

8. An information processing device comprising a processor for receiving a first clock signal, a first device operating in synchronization with the first clock signal, a second device operating in asynchronization with the first clock signal and a bus for connecting the processor, the first device and the second device with each other,

the processor including:

a frequency synthesizer for generating a second clock signal different from the first clock signal based on the first clock signal;

a central processing unit for operating in synchronization with the second clock signal; and

a bus controller for controlling an access to the bus,

the bus controller including;

a detector for receiving an access request from the central processing unit and for detecting whether the access request represents an access to the first device or an access to the second device, the detector including a synchronous clock data storage section having synchronous clock data stored therein indicative of whether an access controlling signal is to be generated in synchronization with the first clock signal or the second clock signal; and

an access controlling signal generator, responsive to the detector, for generating a first access controlling signal for controlling an access of the first device to the bus in synchronization with the first clock signal and for supplying the first access controlling signal to the first device, in a case where the access request represents the access to the first device, the access controlling signal generator generating a second access controlling signal for controlling an access of the second device to the bus in synchronization with the second clock signal and for supplying the second access controlling signal to the second device, in a case where the access request represents the access to the second device.

9. An information processing device according to claim 8, wherein a frequency of the second clock signal is higher than a frequency of the first clock signal.

10. An information processing device according to claim 8, wherein the access request includes at least a part of an address which defines a position to be accessed in the first device and the second device.

11. An information processing device according to claim 8, wherein the synchronous clock data storage section stores a plurality of synchronous clock data, each of the plurality of synchronous clock data determining whether an access to a corresponding address space among a plurality of address spaces is performed in synchronization with the first clock signal or the second clock signal;

and

a selector for selecting one of the plurality of synchronous clock data stored in the synchronous clock data storage section in accordance with an identifying signal for identifying one of the plurality of address spaces.

12. An information processing device according to claim 8, wherein the access controlling signal generator comprises:

a selector for selecting one of the first clock signal and the second clock signal based on a detection result of the detector; and

a generator for generating one of the first access controlling signal and the second access controlling signal based on an output from the selector.

13. An information processing device according to claim 8, further comprising a wait controller for generating a bus cycle ending signal for indicating an end of a bus cycle in synchronization with the second clock signal, and outputting the bus cycle ending signal to the access controlling signal generator.

14. An information processing device according to claim 13, wherein the wait controller comprises:

a wait cycle data storage section for storing a plurality of wait cycle data, each of the plurality of wait cycle data representing a wait cycle number with respect to a corresponding address space among a plurality of address spaces in a cycle unit of the second clock signal;

a selector for selecting one of the plurality of wait cycle data stored in the wait cycle data storage section in accordance with an identifying signal for identifying one of the plurality of address spaces; and

a counter for counting a bus cycle number in a cycle unit of the second clock signal based on an output from the selector, and outputting the bus cycle ending signal in a case where the bus cycle number reaches a predetermined value.