Integrated multi-layer test pads

• US 5,917,197 A
• Filed: 05/21/1997
• Issued: 06/29/1999
• Est. Priority Date: 05/21/1997
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG, International Business Machines Corporation
• Original Assignee: International Business Machines Corporation, Siemens AG
• Inventors: Prein, Frank, Mendelson, Ron, Hoyer, Ronald, Davies, William, Alswede, Frank
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US08/861,465
• Time in Patent Office: 769 Days
• Field of Search: 257/48, 257/758, 257/211, 257/203, 257/923, 324/765, 324/757, 324/766, 324/767, 324/768, 324/769
• US Class Current: 257/48
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: Y10S 257/923 with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Abstract

A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3×3 block of the first pads.

Claims

1. On a semiconductor wafer, a multi-layer test pad configured for electrically coupling with an integrated semiconductor device formed out of said semiconductor wafer, comprising:

an underlying matrix of interconnected first pads, said first pads being configured for electrically coupling with said integrated semiconductor device;

an oxide layer disposed above said underlying matrix;

an overlying matrix of interconnected second pads disposed above said oxide layer, one of said first pads having a first surface area smaller than a second surface area of one of said second pads, said one of said first pads being disposed below and being completely overlapped by said one of said second pads; and

at least one conductive via electrically coupling said underlying matrix with said overlying matrix through said oxide layer.

2. The multi-layer test pad of claim 1 wherein said overlying matrix of interconnected second pads comprises aluminum.

3. The multi-layer test pad of claim 2 wherein said underlying matrix of interconnected first pads comprises tungsten.

4. The multi-layer test pad of claim 1 wherein said overlying matrix of interconnected second pads comprises a plurality of periphery second pads and at least one center second pad, a surface area of said center second pad being at least larger than an area occupied by a 3×

3 block of said first pads, said 3×

3 block of said first pads being disposed below said center second pad.

5. The multi-layer test pad of claim 4 wherein each of said periphery second pads is larger in surface area than said center second pad.

6. The multi-layer test pad of claim 5 further comprising four corner second pads disposed at four corners said multi-layer test pad, each of said four corner second pads being larger than said each of said periphery second pads.

7. The multi-layer test pad of claim 1 wherein said overlying matrix of interconnected second pads comprises a plurality of periphery second pads and at least one center second pad, a surface area of said center second pad being substantially equal to an area occupied by a 3×

3 block of said first pads, said 3×

3 block of said first pads being disposed below said center second pad.

8. The multi-layer test pad of claim 1 further comprising an intermediate metallization layer, said intermediate metallization layer being coupled to both said overlying matrix and said underlying matrix.

9. On a semiconductor wafer, a multi-layer test pad, comprising:

an underlying matrix of interconnected first pads, said first pads being arranged in rows and columns;

an oxide layer disposed above said underlying matrix and in between said rows and columns; and

an overlying matrix of interconnected second pads disposed above said oxide layer, each of said second pads completely overlaps at least nine of said first pads, including four oxide regions surrounding a center first pad of said nine of said first pads, said nine of said first pads being arranged as 3×

3 block of said first pads.

10. The multi-layer test pad of claim 9 wherein said overlying matrix of interconnected second pads comprises aluminum.

11. The multi-layer test pad of claim 10 wherein said underlying matrix of interconnected first pads comprises tungsten.

12. The multi-layer test pad of claim 9 wherein said overlying matrix of interconnected second pads comprises a plurality of periphery second pads and at least one center second pad, said periphery second pads surrounding a periphery of said multi-layer test pad, each of said periphery second pads being at least larger than an area occupied by said 3×

3 block of said first pads.

13. The multi-layer test pad of claim 12 further comprising four corner second pads disposed at four corners of said multi-layer test pad, each of said four corner pads being larger than said each of said periphery second pads.

14. The multi-layer test pad of claim 9 further comprising an intermediate metallization layer, said intermediate metallization layer being coupled to both said overlying matrix and said underlying matrix.