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Stepped edge structure of an EEPROM tunneling window

  • US 5,917,215 A
  • Filed: 09/04/1998
  • Issued: 06/29/1999
  • Est. Priority Date: 06/30/1997
  • Status: Expired due to Term
First Claim
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1. A flash memory MOS field effect transistor device comprising:

  • a) a silicon semiconductor substrate having an upper surface,b) a source region and a drain region formed in said substrate on said upper surface, a channel region between said source and drain regions;

    a tunneling region surrounded by said channeling region;

    c) a gate oxide layer, a stepped tunnel oxide structure and a tunnel oxide layer over the surface of said substrate including said surface over said source and said drain regions, said gate oxide layer surrounding said stepped tunnel oxide structure;

    said stepped tunnel oxide structure surrounding said tunnel oxide layer;

    d) said tunnel oxide structure comprising a tunnel oxide layer surrounded by a stepped tunnel oxide structure;

    said gate oxide layer having a thickness greater than the thickness of said tunnel oxide layer;

    said stepped tunnel oxide structure having n steps where n is between 1 and 5;

    e) a gate structure composed of a stack formed upon said gate oxide layer, said stepped tunneling oxide structure and said tunneling oxide layer; and

    f) said stack comprising a floating gate electrode, a dielectric layer formed upon said floating gate electrode and a control electrode formed upon said dielectric layer.

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