Stepped edge structure of an EEPROM tunneling window

• US 5,917,215 A
• Filed: 09/04/1998
• Issued: 06/29/1999
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chung, Ming-Chih, Lin, Jyh-Feng, Chuang, Kuen-Joung
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Tran, Thien F
• Application Number:
  US09/148,555
• Time in Patent Office: 298 Days
• Field of Search: 257/321, 257/315, 257/327, 438/263, 438/264
• US Class Current: 257/321
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence

Abstract

The present invention provides a structure and a method of forming a stepped trench oxide structure for a semiconductor memory device. The stepped trench oxide structure has "oxide steps" (e.g., 252 or 34A, 34B, 34C) in the gate oxide 20 surrounding the tunnel oxide layer 30. The oxide steps 34 are formed where the oxide thinning effect normally thins the tunnel oxide 30 around the perimeter of the tunnel oxide layer 30. The oxide steps 34 252 compensate for the oxide thinning effect and eliminate the problems associated with the oxide thinning effects. The oxide steps are preferably formed using one photo mask to form two different sized openings using different photoresist exposure times. The preferred method comprises forming a first tunneling opening 220A in a first (gate) oxide layer 220. Then, forming a second oxide layer 250 over said exposed substrate and said first oxide layer 220. A second opening 250A (smaller than the first opening) is formed in the second oxide layer thereby forming a first step 252. Next, a third oxide layer 270 is formed over said exposed substrate, the first oxide layer 220 and the second oxide layer 250 thereby propagating the first step 252. The oxide thinning edge effect is eliminated by the first step.

Claims

1. A flash memory MOS field effect transistor device comprising:

a) a silicon semiconductor substrate having an upper surface,

b) a source region and a drain region formed in said substrate on said upper surface, a channel region between said source and drain regions;

a tunneling region surrounded by said channeling region;

c) a gate oxide layer, a stepped tunnel oxide structure and a tunnel oxide layer over the surface of said substrate including said surface over said source and said drain regions, said gate oxide layer surrounding said stepped tunnel oxide structure;

said stepped tunnel oxide structure surrounding said tunnel oxide layer;

d) said tunnel oxide structure comprising a tunnel oxide layer surrounded by a stepped tunnel oxide structure;

said gate oxide layer having a thickness greater than the thickness of said tunnel oxide layer;

said stepped tunnel oxide structure having n steps where n is between 1 and 5;

e) a gate structure composed of a stack formed upon said gate oxide layer, said stepped tunneling oxide structure and said tunneling oxide layer; and

f) said stack comprising a floating gate electrode, a dielectric layer formed upon said floating gate electrode and a control electrode formed upon said dielectric layer.

2. The flash memory MOS field effect transistor device of claim 1 wherein said tunnel oxide layer has a thickness in a range of between about 50 and 150 Å

.

3. The flash memory MOS field effect transistor device of claim 1 wherein said stepped tunneling structure having a first step with a thickness in a range of between about 100 and 150 Å

and a width in a range between about 0.02 and 0.07 μ

m.