Trenched field effect transistor with PN depletion barrier

• US 5,917,216 A
• Filed: 10/31/1996
• Issued: 06/29/1999
• Est. Priority Date: 02/10/1995
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, Floyd, Brian H., Chang, Mike F., Pitzer, Dorman C.
• Primary Examiner(s): FAHMY, WAEL M
• Application Number:
  US08/742,326
• Time in Patent Office: 971 Days
• Field of Search: 257/330, 257/331, 257/332, 257/333, 257/334, 257/403
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate

Abstract

A trenched MOSFET in its on-state conducts current through an accumulation region and through an inverted depletion barrier layer located along the trench sidewalls. Blocking is achieved by gate control depletion of the adjacent region and by the depletion barrier layer (having the appearance of "ears" in a cross sectional view and being of opposite doping type to the adjacent region) which extends laterally from the trench sidewalls into the drift region. This MOSFET has superior on-state specific resistance to that of prior art trenched MOSFETs and also has good performance in terms of on state resistance, while having superior blocking characteristics to those of prior art trenched MOSFETs. The improvement in the blocking characteristic is provided by the depletion barrier layer which is a semiconductor doped region. In the blocking state, the depletion barrier layer is fully or almost fully depleted to prevent parasitic bipolar conduction. The shape and extent of the depletion barrier layer may be varied and more than one depletion barrier layer may be present.

Claims

1. A field effect transistor formed in a semiconductor material having a first conductivity type and having a principal surface, and comprising:

at least two trenches, spaced apart from one another, each trench extending into the semiconductor material from the principal surface;

a conductive gate electrode of a second conductivity type in each trench;

a source region of the first conductivity type and extending into the semiconductor material from the principal surface, between the two trenches; and

a barrier region associated with each of the trenches and being of the second conductivity type, and in contact with the semiconductor material and underlying the source region and wherein each barrier region extends from a sidewall of the associated trench towards the barrier region associated with the other trench, there being a portion of the semiconductor material of the first conductivity type laterally spacing apart the barrier regions and wherein each barrier region is located intermediate a floor of the associated trench and the principal surface, wherein each barrier region is electrically floating and is insulated from the gate electrode and has no voltage impressed thereon and is spaced apart from the source region.

2. The field effect transistor of claim 1, wherein each barrier region extends only part way between the source region and a floor of the associated trench.

3. The field effect transistor of claim 1, each barrier region having a doping concentration in a range of 10¹³ to 10¹⁸ /cm³.

4. The transistor of claim 1, wherein the source region is in two spaced apart portions, and further comprising:

a region of the second conductivity type lying between the two portions of the source region, and

a region of the second conductivity type lying between the two portions of the first barrier region.

5. The transistor of claim 1, wherein the source region is in two spaced apart portions.

6. The transistor of claim 1,

wherein the semiconductor material comprises a lower portion and an upper portion, the lower portion being more heavily doped than the upper portion and the trenches extending to and not into the lower portion.

7. The transistor of claim 1, wherein the semiconductor material comprises a lower portion and an upper portion, the lower portion being more heavily doped than the upper portion, the trenches extending into the upper portion and being spaced apart from the lower portion.

8. The transistor of claim 1, wherein the semiconductor material comprises a lower portion and an upper portion, the lower portion being more heavily doped than the upper portion, the trenches extending into the lower portion.

9. The transistor of claim 1, further comprising a termination laterally surrounding an active portion of the transistor at the principal surface, the termination isolating the active portion of the transistor.

10. A field effect transistor formed in a semiconductor material having a first conductivity type and having a principal surface, and comprising:

at least two trenches, spaced apart from one another, each trench extending into the semiconductor material from the principal surface;

a conductive gate electrode in each trench;

a substrate region underlying the trenches and doped to have the first conductivity type to a greater doping concentration than the semiconductor material;

a source region of the first conductivity type and extending into the semiconductor material from the principal surface, between the two trenches and of greater doping concentration than the semiconductor material; and

a barrier region associated with each of the trenches and being of a second opposite conductivity type and in the semiconductor material underlying and spaced apart from the source region and wherein each barrier region extends from a sidewall of the associated trench and towards the barrier region associated with the other trench, there being a portion of the semiconductor material of the first conductivity type laterally spacing apart the barrier regions and wherein each barrier region is located intermediate a floor of the trench and the principal surface, the barrier region having a doping concentration substantially less than that of the substrate region and being electrically floating, there being no voltage impressed thereon.

11. A field effect transistor formed in a semiconductor material having a first conductivity type and having a principal surface, and comprising:

at least two trenches, spaced apart from one another, each trench extending into the semiconductor material from the principal surface;

a conductive gate electrode of a second opposite conductivity type in each trench;

a source region of the first conductivity type and extending into the semiconductor material from the principal surface, between the two trenches;

a first barrier region of the second conductivity type in contact with the semiconductor material and underlying the source region and between the two trenches, wherein the first barrier region is electrically insulated from the gate electrode and is spaced apart from the source region; and

a second barrier region of the second conductivity type in the semiconductor material below the source region and between the two trenches, and spaced apart from the first barrier region and located nearer the source region than is the first barrier region.

12. The field effect transistor of claim 11, wherein the first barrier region is in two portions, each portion extending from a sidewall of one of the trenches.

13. The transistor of claim 11, wherein the first barrier region extends from a sidewall of a first of the two trenches to a sidewall of a second of the two trenches.

14. The transistor of claim 11, wherein the first barrier region is in two portions, a first portion adjacent a sidewall of a first of the two trenches and the second portion adjacent a sidewall of the second of the two trenches.