Insulated gate field effect transistor having specific dielectric structures

• US 5,917,225 A
• Filed: 09/26/1996
• Issued: 06/29/1999
• Est. Priority Date: 03/05/1992
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko, Yamazaki, Shunpei, Zhang, Hongyong
• Primary Examiner(s): Hardy, David B.
• Application Number:
  US08/721,052
• Time in Patent Office: 1,006 Days
• Field of Search: 257/410, 257/411, 257/72, 257/59, 257/406, 257/347, 438/151, 438/216, 438/287, 438/591
• US Class Current: 257/411
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device

Abstract

In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate electrode and the gate insulating film to prevent invasion of movable ions into a channel, and also to prevent the breakdown of the gate insulating film due to a potential difference between the gate electrode and the channel region. By coating a specific portion of the gate electrode with metal material such as chrome or the like for the anodic oxidation, and then removing only the metal material such as chrome or the like together with the anodic oxide of the metal material such as chrome or the like, an exposed portion of metal gate (e.g. aluminum) is formed, and an upper wiring is connected to the exposed portion. Further, an aluminum oxide or silicon nitride is formed as an etching stopper between the gate electrode and the gate insulating film or between the substrate and the layer on the substrate, so that the over-etching can be prevented and the flatness of the element can be improved. In addition, a contact is formed in no consideration of the concept "contact hole".

Claims

1. An insulated gate thin film transistor comprising:

a semiconductor layer comprising crystalline silicon formed on an insulating surface of a substrate;

a channel region formed within said semiconductor layer;

source and drain regions formed within said semiconductor layer with said channel region therebetween;

a first insulating film comprising silicon oxide formed on said channel region;

a second insulating film formed on said first insulating film; and

a gate electrode formed over said channel region with said first and second insulating films interposed therebetween,

said transistor characterized in that said second insulating film comprises a material selected from the group consisting of silicon nitride and aluminum oxide, and that said second insulating film extends beyond side edges of said gate electrode but does not cover a major surface of said source and drain regions,

wherein said first insulating film is thicker than said second insulating film.

2. The transistor of claim 1 wherein said material of the second insulating film is silicon nitride.

3. The insulated gate thin film transistor according to claim 1 wherein the thickness of said first insulating film is 50 to 200 nm.

4. The insulated gate thin film transistor according to claim 3 wherein the thickness of said second insulating film is 2 to 50 nm.

5. An insulated gate thin film transistor comprising:

a semiconductor layer comprising crystalline silicon formed on an insulating surface of a substrate;

a channel region formed within said semiconductor layer;

source and drain regions formed within said semiconductor layer with said channel region therebetween;

a first insulating film comprising silicon oxide formed on said channel region;

a second insulating film formed on said first insulating film; and

a gate electrode formed over said channel region with said first and second insulating films interposed therebetween,

said transistor characterized in that said second insulating film comprises a material selected from the group consisting of silicon nitride and aluminum oxide, and that said first insulating film is thicker than said second insulating film.

6. The transistor of claim 5 wherein said material of the second insulating film is silicon nitride.

7. The transistor of claim 5 wherein said first and second insulating films are coextensive with each other.

8. The insulated gate thin film transistor according to claim 5 wherein the thickness of said first insulating film is 50 to 200 nm.

9. The insulated gate thin film transistor according to claim 8 wherein the thickness of said second insulating film is 2 to 50 nm.

10. An insulated gate thin film transistor comprising:

a semiconductor layer comprising crystalline silicon formed on an insulating surface of a substrate;

a channel region formed within said semiconductor layer;

source and drain regions formed within said semiconductor layer with said channel region therebetween;

a first insulating film comprising silicon oxide formed on said channel region;

a second insulating film formed on said first insulating film wherein said first insulating film is thicker than said second insulating film; and

a gate electrode formed over said channel region with said first and second insulating films interposed therebetween,

said transistor characterized in that said second insulating film comprises a material selected from the group consisting of silicon nitride and aluminum oxide, and that said second insulating film extends beyond side edges of said gate electrode but does not cover a major surface of said source and drain regions while said first insulating film covers the major surface of said source and drain regions except for contact portions thereof.

11. The transistor of claim 10 wherein said material of the second insulating film is silicon nitride.

12. The insulated gate thin film transistor according to claim 10 wherein the thickness of said first insulating film is 50 to 200 nm.

13. The insulated gate thin film transistor according to claim 12 wherein the thickness of said second insulating film is 2 to 50 nm.

14. An insulated gate field effect transistor comprising:

a semiconductor layer comprising crystalline silicon formed on an insulating surface of a substrate;

a channel region formed within said semiconductor layer;

source and drain regions formed within said semiconductor layer with said channel region therebetween;

a gate insulating film formed on said semiconductor layer; and

a gate electrode formed over said channel region with said gate insulating film interposed therebetween,

said transistor characterized in that said gate insulating film comprises at least a first insulating film comprises silicon oxide and a second insulating film comprises silicon nitride which is thinner than said first insulating film, and that at least said second insulating film extends beyond side edges of said gate electrode to cover a part of said source and drain regions.

15. The insulated gate field effect transistor according to claim 14 wherein the thickness of said first insulating film is 50 to 200 nm.

16. The insulated gate field effect transistor according to claim 15 wherein the thickness of said second insulating film is 2 to 50 nm.

17. An insulated gate field effect transistor comprising:

a semiconductor layer comprising crystalline silicon formed on an insulating surface of a substrate;

a channel region formed within said semiconductor layer;

source and drain regions formed within said semiconductor layer with said channel region therebetween;

a gate insulating film formed on said semiconductor layer; and

a gate electrode formed over said channel region with said gate insulating film interposed therebetween,

said transistor characterized in that said gate insulating film comprises at least a first insulating film comprises silicon oxide and a second insulating film comprises silicon nitride, that said first insulating film is thicker than said second insulating film.

18. The insulated gate field effect transistor according to claim 17 wherein the thickness of said first insulating film is 50 to 200 nm.

19. The insulated gate field effect transistor according to claim 18 wherein the thickness of said second insulating film is 2 to 50 nm.

20. An insulated gate field effect transistor comprising:

a semiconductor layer comprising crystalline silicon formed over a substrate;

a channel region formed within said semiconductor layer;

a pair of impurity regions formed within said semiconductor layer with said channel region therebetween;

a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and

a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween,

wherein at least said second insulating film extends beyond side edges of the gate electrode,

wherein said first insulating film is thicker than said second insulating film.

21. An insulated gate field effect transistor according to claim 20 wherein said pair of impurity regions are source and drain regions of the transistor.

22. An insulated gate field effect transistor according to claim 20 wherein said gate electrode is located over said channel region.

23. An insulated gate field effect transistor according to claim 20 wherein said silicon nitride film is in direct contact with said gate electrode.

24. The insulated gate field effect transistor according to claim 20 wherein the thickness of said first insulating film is 50 to 200 nm.

25. The insulated gate field effect transistor according to claim 24 wherein the thickness of said second insulating film is 2 to 50 nm.

41. The insulated gate field effect transistor according to claim 20 wherein said semiconductor film is 20 to 100 nm thick.

26. An insulated gate field effect transistor comprising:

a semiconductor layer comprising crystalline silicon formed over a substrate;

a channel region formed within said semiconductor layer;

a pair of impurity regions formed within said semiconductor layer with said channel region therebetween;

a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and

a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween,

wherein said first insulating film is thicker than said second insulating film.

27. An insulated gate field effect transistor according to claim 26 wherein said pair of impurity regions are source and drain regions of the transistor.

28. An insulated gate field effect transistor according to claim 26 wherein said gate electrode is located over said channel region.

29. An insulated gate field effect transistor according to claim 26 wherein said silicon nitride film is in direct contact with said gate electrode.

30. The insulated gate field effect transistor according to claim 26 wherein the thickness of said first insulating film is 50 to 200 nm.

31. The insulated gate field effect transistor according to claim 30 wherein the thickness of said second insulating film is 2 to 50 nm.

42. The insulated gate field effect transistor according to claim 26 wherein said semiconductor film is 20 to 100 nm thick.

32. An insulated gate field effect transistor comprising:

a semiconductor layer comprising crystalline silicon formed over a substrate;

a channel region formed within said semiconductor layer;

a pair of impurity regions formed within said semiconductor layer with said channel region therebetween;

a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising aluminum oxide; and

a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween,

wherein, said first insulating film is thicker than said second insulating film.

33. An insulated gate field effect transistor according to claim 32 wherein said pair of impurity regions are source and drain regions of the transistor.

34. An insulated gate field effect transistor according to claim 32 wherein said gate electrode is located over said channel region.

35. An insulated gate field effect transistor according to claim 34 wherein said silicon nitride film is in direct contact with said gate electrode.

40. The insulated gate field effect transistor according to claim 32 wherein the thickness of said first insulating film is 50 to 200 nm while the thickness of said second insulating film is 2 to 50 nm.

43. The insulated gate field effect transistor according to claim 32 wherein said semiconductor film is 20 to 100 nm thick.

36. An insulated gate field effect transistor comprising:

a semiconductor layer comprising crystalline silicon formed over a substrate;

a channel region formed within said semiconductor layer;

a pair of impurity regions formed within said semiconductor layer with said channel region therebetween;

a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and

a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween,

wherein at least said second insulating film extends beyond side edges of the gate electrode,

wherein said first insulting film is thicker than said second insulating film and the thickness of said first insulating film is 50 to 200 nm.

37. An insulated gate field effect transistor comprising:

a semiconductor layer comprising crystalline silicon formed over a substrate;

a channel region formed within said semiconductor layer;

a pair of impurity regions formed within said semiconductor layer with said channel region therebetween;

a gate insulating film adjacent to said semiconductor layer, including at least a first insulting film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and

a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween,

wherein at least said second insulating film extends beyond side edges of the gate electrode,

wherein said first insulating film is thicker than said second insulating film and the thickness of said second insulating film is 2 to 50 nm.

38. An insulated gate field effect transistor comprising:

a semiconductor layer comprising crystalline silicon formed over a substrate;

a channel region formed within said semiconductor layer;

a pair of impurity regions formed within said semiconductor layer with said channel region therebetween;

a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and

a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween,

wherein said first insulating film is thicker than said second insulating film and the thickness of said first insulating film is 50 to 200 nm.

39. An insulated gate field effect transistor comprising:

a semiconductor layer comprising crystalline silicon formed over a substrate;

a channel region formed within said semiconductor layer;

a pair of impurity regions formed within said semiconductor layer with said channel region therebetween;

a gate insulating film adjacent to said semiconductor layer, including at least a first insulating film comprising silicon oxide in contact with said channel region and a second insulating film comprising silicon nitride film; and

a gate electrode adjacent to said channel region with said gate insulating film interposed therebetween,

wherein said first insulating film is thicker than said second insulating film and the thickness of said second insulating film is 2 to 50 nm.