BiMOS integrated circuit

• US 5,917,342 A
• Filed: 03/29/1996
• Issued: 06/29/1999
• Est. Priority Date: 03/31/1995
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Okamura, Hitoshi
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/623,834
• Time in Patent Office: 1,187 Days
• Field of Search: 326/109-110, 326/101-103, 257/204-206, 257/401, 257/378
• US Class Current: 326/103
• CPC Class Codes: H01L 27/11896 using combined field effect/bipolar technology

Abstract

A BiMOS integrated circuit includes a bipolar transistor for output pull-up; a BiMOS hybrid gate buffer section which comprises a MOS transistor for output pull-down which is longitudinally connected to the bipolar transistor, and a MOS transistor for base drive which comprises an output which is connected a base of the bipolar transistor to drive the base and a gate which is connected to an input; and a logical section which comprises at least a CMOS gate, the logical section having an output which is connected to the input; wherein the base drive MOS transistor has an input capacitance less than that of the output pull-down MOS transistor.

Claims

1. A BiMOS integrated circuit disposed on a semiconductor substrate, comprising:

an input terminal;

an output terminal;

a bipolar-MOS hybrid gate section which includes,

an output pullup section which includes a bipolar transistor, said bipolar transistor having a base, a collector and a source, said source being connected to said output terminal, said bipolar transistor being buried in a first region on said semiconductor substrate; and

an output pulldown section which includes a first MOS transistor, said first MOS transistor connected in series with said bipolar transistor, said first MOS transistor having a gate, source and a drain, said drain being connected to said output terminal, said first MOS transistor being formed by connecting in parallel two MOS transistors having equal gate widths that are buried in a first diffusion region on said semiconductor substrate; and

a CMOS gate section which includes a second MOS transistor having a gate, a source and a drain, and a third MOS transistor having a gate, a source and a drain, said third MOS transistor being connected in series with said second MOS transistor, said gates of said second and third MOS transistors being connected to said input terminal and said drains of said second and third MOS transistors being connected to said base of said bipolar transistor, said CMOS gate section connected between said input terminal and said base of said bipolar transistor, said second MOS transistor being buried in a second diffusion region on said semiconductor substrate with a fourth MOS transistor having an equal gate width, said third MOS transistor being buried in a third diffusion region on said semiconductor substrate with a fifth MOS transistor having an equal gate width less than that of each of said second and fourth MOS transistors,

wherein said second MOS transistor has an input capacitance less than that of said first MOS transistor,

wherein said BiMOS integrated circuit is fabricated by a master-slice manner in which a basic cell array comprised of a plurality of transistors is disposed on a semiconductor substrate and said plurality of transistors are interconnected to implement a given logical function, and

wherein said gate of said third MOS transistor is connected to said gate of said first MOS transistor, said third MOS transistor also functioning as part of said output pulldown section.

2. A BiMOS integrated circuit according to claim 1, wherein said second and third MOS transistors provide a base drive for said bipolar transistor.

3. A BiMOS integrated circuit according to claim 1, wherein said gate of said first MOS transistor is connected to said input terminal and said source of said first MOS transistor is connected to ground, and

wherein said gate of said third MOS transistor is connected to said input terminal and said source of said third MOS transistor is connected to said ground.

4. A BiMOS integrated circuit according to claim 3, wherein said second MOS transistor is of a first conductivity type, said third MOS transistor is of a second conductivity type, and said first MOS transistor is of the second conductivity type.

5. A BiMOS integrated circuit according to claim 1, wherein said first, second and third MOS transistors have a same gate length and a same gate silicon oxide film thickness, and

wherein a sum of gate widths of said second and third MOS transistors is less than a gate width of said first MOS transistor.

6. A BiMOS integrated circuit according to claim 2, wherein said first, second and third MOS transistors have a same gate length and a same gate silicon oxide film thickness, and

wherein a sum of gate widths of said second and third MOS transistors is less than a gate width of said first MOS transistor.

7. A BiMOS integrated circuit according to claim 3, wherein said first, second and third MOS transistors have a same gate length and a same gate silicon oxide film thickness, and

wherein a sum of gate widths of said second and third MOS transistors is less than a gate width of said first MOS transistor.

8. A BiMOS integrated circuit according to claim 1, wherein a total occupied area of said bipolar-MOS hybrid gate section on said semiconductor substrate is less than an occupied area of said CMOS gate section on said semiconductor substrate.

9. A BiMOS integrated circuit according to claim 1, wherein second MOS transistor is PMOS and said third MOS transistor is NMOS, thereby forming said CMOS gate section.

10. A BiMOS integrated circuit according to claim 1, wherein said first MOS transistor is connected in parallel with said third MOS transistor to realize a pulldown function for said BiMOS integrated circuit.

11. A BiMOS integrated circuit according to claim 1, wherein said third MOS transistor is buried in an interconnection region on said semiconductor substrate, said interconnection region corresponding to said third diffusion region and being located between cell array rows disposed on said semiconductor substrate.

12. A BiMOS integrated circuit according to claim 5, wherein the gate width of said second MOS transistor is greater than the gate width of said third MOS transistor.

13. A BiMOS integrated circuit according to claim 1, wherein said CMOS gate section includes said two MOS transistors buried in the first diffusion region, said second MOS transistor and said third MOS transistor,

wherein said bipolar-MOS hybrid gate section includes said two MOS transistors buried in the first diffusion region, and

wherein said two MOS transistors buried in the first diffusion region operate in both the CMOS gate section and said bipolar-MOS hybrid gate section.

14. A BiMOS flip-flop comprising:

an input terminal;

an output terminal;

a first CMOS inverter having an input connected to said input terminal and an output; and

a second CMOS inverter having an input connected to said output of said first CMOS inverter, said second CMOS inverter having an output connected to said input of said first CMOS inverter;

a third CMOS inverter having an input connected to said output terminal and an output; and

a Bi-MOS inverter connected in parallel with said third CMOS inverter, said Bi-MOS inverter including,

a bipolar-MOS hybrid gate section which includes,

an output pullup section which includes a bipolar transistor, said bipolar transistor having a base, a collector and a source, said source being connected to said output terminal; and

an output pulldown section which includes a first MOS transistor, said first MOS transistor connected in series with said bipolar transistor, said first MOS transistor having a gate, source and a drain, said drain being connected to said output terminal, said first MOS transistor being formed by connecting in parallel two MOS transistors buried in a same diffusion region and having a same gate width; and

a CMOS gate section which includes a second MOS transistor having a gate, a source and a drain, and a third MOS transistor having a gate, a source and a drain, said third MOS transistor being connected in series with said second MOS transistor, said gates of said second and third MOS transistors being connected to said input terminal and said drains of said second and third MOS transistors being connected to said base of said bipolar transistor,

wherein said second MOS transistor has an input capacitance less than that of said first MOS transistor,

wherein said BiMOS flip-flop is fabricated by a master-slice manner in which a basic cell array comprised of a plurality of transistors is disposed on a semiconductor substrate and said plurality of transistors are interconnected to implement a given logical function, and

wherein said gate of said third MOS transistor is connected to said gate of said first MOS transistor, said third MOS transistor also functioning as part of said output pulldown section.

15. A gate array disposed on a semiconductor substrate, comprising:

an NPN bipolar transistor buried in a first region on said semiconductor substrate;

first and second NMOS transistors buried in a first diffusion region on said semiconductor substrate and having a same gate width;

third and fourth NMOS transistors buried in a second diffusion region on said semiconductor substrate and having the same gate width as said first and second NMOS transistors, the first through fourth NMOS transistors corresponding to an SRAM structure on said semiconductor substrate; and

fifth and sixth NMOS transistors buried in a third diffusivity region on said semiconductor substrate and having a same gate width different from the gate width of said first through fourth NMOS transistors,

wherein a BiNMOS gate array is formed by providing a bipolar-MOS hybrid gate section with said NPN bipolar transistor and one of said fifth and sixth NMOS transistors, and an SRAM section with one of said first through fourth NMOS transistors.