Three state phase detector

• US 5,917,356 A
• Filed: 09/11/1995
• Issued: 06/29/1999
• Est. Priority Date: 09/11/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nguyen, Trong Duc, Li, Hehching Harry, Casal, Humberto Felipe
• Primary Examiner(s): CUNNINGHAM, TERRY D
• Application Number:
  US08/526,395
• Time in Patent Office: 1,387 Days
• Field of Search: 327/2, 327/3, 327/5, 327/7, 327/10, 327/12, 327/155, 327/156, 327/158, 327/159, 327/270, 327/276, 327/234, 327/236
• US Class Current: 327/236
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence

Abstract

A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.

Claims

1. A circuit, comprising:

means for receiving a first pulse of a first digital signal;

means for receiving a second pulse of a second digital signal;

means for determining if said first and second pulses are synchronized within a predetermined tolerance value; and

means for determining which of said first and second pulses is leading the other, wherein said means for determining if said first and second pulses are synchronized within said predetermined tolerance value further comprises;

a first latch circuit having an input coupled to said means for receiving said second pulse of said second digital signal;

a first delay circuit coupled between said means for receiving said first pulse of said first digital signal and a clock input to said first latch circuit;

a second latch circuit having a clock input coupled to said means for receiving said first pulse of said first digital signal;

a second delay circuit coupled between said means for receiving said second pulse of said second digital signal and an input to said second latch circuit; and

an XOR circuit having a first input coupled to an output of said first latch circuit and a second input coupled to an output of said second latch circuit.

2. The circuit as recited in claim 1, wherein said means for determining which of said first and second pulses is leading the other further comprises:

a latch circuit having a clock input coupled to said means for receiving said first pulse of said first digital signal and an input coupled to said means for receiving said second pulse of said second digital signal.

3. The circuit as recited in claim 1, wherein said first and second delay circuits determine said predetermined tolerance value.

4. A circuit for adjusting skew in a digital clock signal, comprising:

means operable for receiving said clock signal;

means operable for transmitting said clock signal to a logic circuitry;

means operable for receiving from said logic circuitry a feedback signal associated with said clock signal;

means operable for determining if said clock signal and said feedback signal are synchronized within a predetermined tolerance value;

means operable for determining which of said clock signal and said feedback signal is leading the other;

means operable for removing delay from said feedback signal and said clock signal when said feedback signal is lagging said clock signal, wherein said means operable for removing delay from said feedback signal and said clock signal is coupled to said means for determining which of said clock signal and said feedback signal is leading the other and coupled to said means for determining if said clock signal and said feedback signal are synchronized; and

means operable for delaying said feedback signal and said clock signal when said feedback signal is leading said clock signal, wherein said means operable for delaying said feedback signal and said clock signal is coupled to said means for determining which of said clock signal and said feedback signal is leading the other, and coupled to said means for determining if said clock signal and said feedback signal are synchronized.

5. The circuit as recited in claim 4, wherein said means operable for determining if said clock signal and said feedback signal are synchronized within said predetermined tolerance value further comprises:

a first latch circuit having an input coupled to said means operable for receiving said feedback signal;

a first delay circuit coupled between said means operable for receiving said clock signal and a clock input to said first latch circuit;

a second latch circuit having a clock input coupled to said means operable for receiving said clock signal;

a second delay circuit coupled between said means operable for receiving said feedback signal and an input to said second latch circuit; and

an XOR circuit having a first input coupled to an output of said first latch circuit and a second input coupled to an output of said second latch circuit.

6. The circuit as recited in claim 4, wherein said means for determining which of said clock signal and said feedback signal is leading the other further comprises:

a latch circuit having a clock input coupled to said means operable for receiving said clock signal and an input coupled to said means operable for receiving said feedback signal.

7. The circuit as recited in claim 5, wherein said first and second delay circuits determine said predetermined tolerance value.

8. The circuit as recited in claim 4, wherein said means for delaying said clock signal further comprises a third delay circuit operable for receiving said clock signal, wherein an output of said third delay circuit is coupled to said transmitting means, and wherein said means for delaying said feedback signal is coupled to said means operable for receiving said feedback signal and coupled to said logic circuitry.

9. A data processing system comprising:

a processor coupled to a storage device, a memory device, an input device, and an output device via a bus, said processor further comprising;

a clock source for producing a clock signal for use within logic circuitry in said processor;

means operable for receiving said clock signal;

means operable for transmitting said clock signal to said logic circuitry;

means operable for receiving from said logic circuitry a feedback signal associated with said clock signal;

means operable for determining if said clock signal and said feedback signal are synchronized within a predetermined tolerance value;

means operable for determining which of said clock signal and said feedback signal is leading the other;

means operable for removing delay from said feedback signal and said clock signal when said feedback signal is lagging said clock signal, wherein said means operable for removing delay is coupled to said means for determining which of said clock signal and said feedback signal is leading the other; and

means operable for delaying said feedback signal and said clock signal when said feedback signal is leading said clock signal, wherein said means operable for delaying is coupled to said means for determining which of said clock signal and said feedback signal is leading the other.

10. The circuit as recited in claim 9, wherein said means for delaying said clock signal further comprises a third delay circuit operable for receiving said clock signal, wherein an output of said third delay circuit is coupled to said transmitting means, and wherein said means for delaying said feedback signal is coupled to said means operable for receiving said feedback signal and coupled to said logic circuitry.

11. The circuit as recited in claim 10, wherein said means operable for determining if said clock signal and said feedback signal are synchronized within said predetermined tolerance value further comprises:

a first latch circuit having an input coupled to said means operable for receiving said feedback signal;

a first delay circuit coupled between said means operable for receiving said clock signal and a clock input to said first latch circuit;

a second latch circuit having a clock input coupled to said means operable for receiving said clock signal;

a second delay circuit coupled between said means operable for receiving said feedback signal and an input to said second latch circuit; and

an XOR circuit having a first input coupled to an output of said first latch circuit and a second input coupled to an output of said second latch circuit.

12. The circuit as recited in claim 11, wherein said means for determining which of said clock signal and said feedback signal is leading the other further comprises:

a third latch circuit having a clock input coupled to said means operable for receiving said clock signal and an input coupled to said means operable for receiving said feedback signal.

13. The circuit as recited in claim 12, wherein said first and second delay circuits determine said predetermined tolerance value.