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Bi-directional interface circuit of reduced signal alteration

  • US 5,917,364 A
  • Filed: 12/23/1997
  • Issued: 06/29/1999
  • Est. Priority Date: 12/25/1996
  • Status: Expired due to Term
First Claim
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1. A bi-directional interface circuit of reduced signal alteration provided on a LSI chip;

  • said interface circuit comprising;

    an encoder circuit for generating an output bit sequence to be transferred to bus lines in synchronous with a clock cycle of the bus lines, said output bit sequence being obtained by coding an original signal to be transferred and a redundant bit so that signal alteration rate of said output bit sequence to a preceding bit sequence thereof transmitted on the bus lines is less than a half;

    an output buffer for driving the bus lines according to said output bit sequence;

    an input buffer for receiving an input bit sequence transmitted on the bus lines;

    a decoder for decoding said input bit sequence into an original bit sequence to be received; and

    bypass lines for bypassing said input bit sequence to said encoder for enabling said encoder to refer to said input bit sequence as said preceding bit sequence when the LSI chip begins first to transfer said original signal after receiving a signal.

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