Bi-directional interface circuit of reduced signal alteration

• US 5,917,364 A
• Filed: 12/23/1997
• Issued: 06/29/1999
• Est. Priority Date: 12/25/1996
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Nakamura, Kazuyuki
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US08/997,664
• Time in Patent Office: 553 Days
• Field of Search: 365/4, 365/81, 365/89, 365/230.06, 341/160, 341/161, 341/143, 341/51, 326/30, 326/105, 327/141, 327/291, 327/293, 327/595, 327/415
• US Class Current: 327/415
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents

Abstract

To provide a bi-directional interface circuit which can reduce the simultaneous switching noise and the power consumption even at transitions of the signal direction, a bi-directional interface circuit of the invention comprises: an encoder (10) for generating an output bit sequence in synchronous with a clock cycle of the bus lines, said output bit sequence being obtained by coding an original signal and a redundant bit so that signal alteration rate of the output bit sequence to a preceding bit sequence thereof is less than a half; a decoder (20) for decoding the input bit sequence into an original bit sequence; and bypass lines (3) for bypassing the input bit sequence to the encoder for enabling the encoder to refer to the input bit sequence as the preceding bit sequence when the LSI chip begins to transfer the original signal. By providing a first encoder for generating an intermediate bit sequence having less than half logic `1` bits, and a second encoder for switching bit logic when corresponding bit of the intermediate bit sequence is logic `1`, the signal delay of the bypassed input bit sequence can be reduced and I/O clock frequency is not restricted.

Claims

1. A bi-directional interface circuit of reduced signal alteration provided on a LSI chip;

said interface circuit comprising;

an encoder circuit for generating an output bit sequence to be transferred to bus lines in synchronous with a clock cycle of the bus lines, said output bit sequence being obtained by coding an original signal to be transferred and a redundant bit so that signal alteration rate of said output bit sequence to a preceding bit sequence thereof transmitted on the bus lines is less than a half;

an output buffer for driving the bus lines according to said output bit sequence;

an input buffer for receiving an input bit sequence transmitted on the bus lines;

a decoder for decoding said input bit sequence into an original bit sequence to be received; and

bypass lines for bypassing said input bit sequence to said encoder for enabling said encoder to refer to said input bit sequence as said preceding bit sequence when the LSI chip begins first to transfer said original signal after receiving a signal.

2. A bi-directional interface circuit of reduced signal alteration provided on a LSI chip;

said interface circuit comprising;

a first encoder for generating an intermediate output bit sequence in synchronous with a clock cycle of bus lines, said intermediate output bit sequence being an original output bit sequence and a redundant bit of logic `0` when majority bits of said original output bit sequence have logic `0`, and said intermediate output bit sequence being an inverted bit sequence of said original output bit sequence and a redundant bit of logic `1` when majority bits of said original output bit sequence have logic `1`;

a second encoder circuit for generating an output bit sequence whereof signal alteration rate is less than a half, each bit of said output bit sequence having XOR logic of respective bits of said intermediate output bit sequence and a preceding bit sequence threrof transmitted on the bus lines;

an output buffer for driving the bus lines according to said output bit sequence;

an input buffer for receiving an input bit sequence transmitted on the bus lines;

a second decoder for decoding said input bit sequence into an intermediate input bit sequence, each bit of said intermediate input bit sequence having XOR logic of respective bits of said input bit sequence and a preceding bit sequence thereof transmitted on the bus lines;

a first decoder for decoding said intermediate input bit sequence into an original input bit sequence to be received, by outputting bits of said intermediate input bit sequence other than said redundant bit as they are when logic of said redundant bit is `0`, and inverting bits of said intermediate input bit sequence other than said redundant bit when logic of said redundant bit is `1`; and

bypass lines for bypassing said input bit sequence to said second encoder for enabling said second encoder to refer to said input bit sequence as said preceding bit sequence when the LSI chip begins first to transfer said output signal after receiving a signal.