Compact voltage controlled ring oscillator with quadrature outputs

• US 5,917,383 A
• Filed: 11/26/1997
• Issued: 06/29/1999
• Est. Priority Date: 11/26/1997
• Status: Expired due to Term

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Tso, Robert, Herman, Ray Michael
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US08/979,191
• Time in Patent Office: 580 Days
• Field of Search: 331/57, 331/135, 331/177 R
• US Class Current: 331/57
• CPC Class Codes: H03F 2203/45402 the CMCL comprising a buffered addition circuit, i.e. the signals are buffered before addition, e.g. by a follower
• CPC Class Codes: H03F 2203/45418 the CMCL comprising a resistor addition circuit
• CPC Class Codes: H03F 2203/45432 the CMCL output control signal being a current signal and being buffered before used to control
• CPC Class Codes: H03F 2203/45496 the CSC comprising one or more extra resistors
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 3/45511 Controlling the loading circuit of the differential amplifier
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence

Abstract

The compact voltage controlled ring oscillator includes two variable delay gates (VDGs). Each input port of one variable delay gate is connected to the output port of the other variable delay gate to form a feedback loop. A control interface receives an input voltage control signal (VCON), and generates a limited and buffered voltage control signal VX, which is provided to each of the VDGs to generate VDG bias currents which are limited and monotonic with VCON. Each VDG comprises a fixed bias differential transconductance gain stage (GM1), a variable bias differential transconductance hysteresis feedback stage (GM2), and a variable bias voltage follower stage. The combination of delay control from variable hysteresis and variable voltage follower output resistance provides a compact, low power ring oscillator VCO, with over an octave of tuning range.

Claims

1. A compact voltage controlled ring oscillator comprising:

a first variable delay gate and a second variable delay gate, each of the variable delay gates comprising;

an input port to receive a differential input signal;

an output port to transmit a differential output signal;

a fixed bias differential transconductance gain stage (GM1) coupled to the input port to receive the differential input signal and generate correspondingly a differential output current;

a variable bias differential transconductance hysteresis feedback stage (GM2) having a pair of differential input terminals coupled to a first and a second voltage follower amplifier (G3 and G4) to provide a local positive feedback loop, where a differential output current of GM2 is coupled to the differential output current of GM1 to form a summation of differential currents;

a pair of load elements which are connected to both a differential output port of GM1 and GM2 to convert the summation of currents to a differential output voltage;

a voltage follower stage, where a pair of voltage follower stage inputs are coupled to the pair of load elements and a pair of voltage follower stage outputs are coupled to the input port of the other variable delay gate;

wherein a variable bias current in the voltage follower stage is controlled to vary directly proportionately to a control voltage VX, and a bias current in the transconductance stage GM2 is controlled to vary inversely proportionately to the control voltage VX, and wherein the input port of one variable delay gate is connected to the output port of the other variable delay gate; and

a control interface (CI) circuit, the control interface circuit receives a VCO input control voltage signal (VCON) and generates correspondingly an output control voltage signal (VX), wherein the control interface circuit is coupled to provide control signal VX to each of the variable delay gates to thereby vary the value of a pair of current sources in the voltage follower stage in opposing direction to the value of a current source in the GM2 stage.

2. A ring oscillator of claim 1 wherein one or more buffers are connected to each output port of each variable delay gate.

3. A ring oscillator of claim 1 wherein one or more resistors couple the current source of the differential transconductance hysteresis feedback stage (GM2) to the pair of current sources of the voltage follower stage, thereby causing the GM2 biasing current to vary inversely with the biasing current sources of the voltage follower stage and varying inversely proportional to the input control signal VCON.

4. A ring oscillator of claim 1 wherein the control interface circuit comprises a non-linear, limiting coupling means between signal VCON and a pair of bias current sources for the voltage follower stage.

5. The ring oscillator of claim 4 where the non-linear, limiting coupling means comprises Darlington pair transistors coupled to a voltage divider string comprised of resistive and non-linear active elements.

6. A ring oscillator of claim 1 wherein the differential transconductance gain stage (GM1) comprises a differential pair bipolar circuit.

7. A ring oscillator of claim 1 wherein the input port of each variable delay gate comprises a non-inverting input and an inverting input, and the output port of each variable delay gate comprises a non-inverting output and an inverting output, and wherein the non-inverting output of one variable delay gate is coupled to the inverting input of the other variable delay gate, while the inverting output of the one variable delay gate is coupled to the non-inverting input of the other variable delay gate to achieve a 180 degree phase inversion of the differential input signal relative to the other variable delay gate.

8. A compact voltage controlled ring oscillator comprising:

a first variable delay gate and a second variable delay gate, each of the variable delay gates comprising;

an input port to receive a differential input signal;

a first differential pair bipolar circuit (GM1) coupled to the input port to receive the differential input signal and generate correspondingly a differential pair output signal;

a second differential pair bipolar circuit (GM2) coupled at a pair of input terminals of GM2 to a pair of output terminals of an emitter follower stage;

a pair of load elements which are connected to both a pair of differential output terminals of GM1 and a pair of differential output terminals of GM2 to convert a summation of currents to a differential output voltage;

wherein a pair of emitter follower stage input terminals are coupled to the pair of load elements and the pair of emitter follower stage output terminals are coupled to the input port of the other variable delay gate;

an output port, wherein a variable bias current in the emitter follower stage is controlled to vary directly proportionately to a control voltage VX, and a bias current in the transconductance stage GM2 is controlled to vary inversely proportionately to the control voltage VX, and wherein the input port of one variable delay gate is connected to the output port of the other variable delay gate; and

a control interface (CI) circuit, the control interface circuit receives a VCO input control voltage signal (VCON) and generates correspondingly an output control voltage signal (VX), wherein the control interface circuit is coupled to provide control signal VX to each of the variable delay gates to thereby vary the value of a pair of current sources in the emitter follower stage in opposing direction to the value of a current source in the GM2 stage.