Peer-to-peer parallel processing graphics accelerator

• US 5,917,502 A
• Filed: 12/05/1996
• Issued: 06/29/1999
• Est. Priority Date: 12/06/1995
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Intergraph Corporation (Hexagon AB)
• Inventors: Terry, Joseph C., Turner, James P., Allison, Cynthia E., Kirkland, Dale L., Ford, Jeffrey S.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/761,104
• Time in Patent Office: 936 Days
• Field of Search: 345/501-503, 345/505, 345/506, 345/520
• US Class Current: 345/505
• CPC Class Codes: G06F 15/7864 on more than one IC chip
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A graphics processing accelerator has a plurality of digital signal processors that each have an output, and an input in communication with a request bus. The digital signal processors are arranged in a peer-to-peer configuration to process, on a cyclical basis, each of a successive series of graphics requests received over a request bus. The graphics processing accelerator also may have a sequencer in communication with each digital signal processor output for ordering graphics requests processed by the digital signal processors.

Claims

1. A graphics processing accelerator comprising:

a. a plurality of digital signal processors, each processor having an input in communication with a request bus and an output, the digital signal processors being arranged in a peer-to-peer configuration so as to process on a cyclical basis each successive graphics request available on a request bus; and

b. a sequencer in communication with each digital signal processor output for ordering graphics requests processed by the digital signal processors;

wherein each of the digital signal processors has a token input and a token output, and the token output of a first one of the digital signal processors is connected to the token input of a second one of the digital signal processors; and

the presence of a control token in the token input of a digital signal processor identifies an active digital signal processor and triggers the processing by such digital signal processor of a graphics request on the request bus and after processing by such digital signal processor, the control token is provided upon the token output so that processing by all of the digital signal processors is controlled at a peer-to-peer level.

2. A graphics accelerator according to claim 1, the graphics accelerator further comprising:

a distinct communication bus between the sequencer and each of the plurality of digital signal processors so that the sequencer can simultaneously receive a processed graphics request from each of the digital signal processors.

3. A graphics accelerator according to claim 1, wherein a token further includes an identifier of the digital signal processor placing the token upon the token output so that a first processor can determine when the token has traveled cyclically to all digital signal processors.

4. A graphics accelerator according to claim 1, further comprising a token identification arrangement for identifying when a token placed by a first digital signal processor upon the token output has traveled cyclically to all digital signal processors.

5. A graphics accelerator according to claim 1, wherein the sequencer further includes:

means for simultaneously receiving the processed graphic requests from each digital signal processor; and

means for outputting to a graphics rendering device each processed request in the order the processed request was received upon the graphics bus.

6. A graphics accelerator according to claim 1, further comprising a workload balancing arrangement, wherein a first processor can reduce its workload by skipping its turn in the processing cycle.

7. A graphics accelerator according to claim 1, wherein a digital signal processor receiving the control token can provide a skip token to the token output so that the processor may skip its having to process the graphics request upon the request bus.

8. A graphics accelerator according to claim 1, wherein the token input and the token output are configured to handle a global token, and wherein receipt by one of the digital signal processors of the global token in its token input causes such processor

to process the graphics request upon the graphics request bus, and

to place the global token on the token output so as to trigger processing of the graphics request by all other processors.

9. A graphics processing accelerator comprising:

a plurality of digital signal processors each processor having an input in communication with a request bus and an output, the digital signal processors being arranged in a peer-to-peer configuration so as to process on a cyclical basis each successive graphics request available on a request bus; and

a sequencer in communication with each digital signal processor output for ordering graphics requests processed by the digital signal processors, the graphics processing accelerator accelerating a graphics request having coordinate data defining a graphics primitive to be processed, the graphics processing accelerator further comprising;

a null processor for detecting coordinate data defining zero-area primitives, wherein such primitives are not output to the graphics processor after processing by the accelerator.

10. A graphics processing accelerator comprising:

a plurality of digital signal processors, each processor having an input in communication with a request bus and an output, the digital signal processors being arranged in a peer-to-peer configuration so as to process on a cyclical basis each successive graphics request available on a request bus; and

a sequencer in communication with each digital signal processor output for ordering graphics requests processed by the digital signal processors, the graphics processing accelerator accelerating a graphics request having coordinate data defining a graphics primitive to be processed, the graphics processing accelerator further comprising;

a screen clipping processor for clipping the coordinate data to a predetermined viewing area, wherein the viewing area can define a region displayed upon a plurality of display monitors.

11. A method for first and second processors to manage an input queue associated with each such processor, the method comprising:

a. receiving a token on a token input of the first processor, the token being associated with a graphics request stored in a computer memory, and wherein the token includes information about the size of the graphics request;

b. reading the token in the token input to determine the size of the graphics request;

c. configuring a direct memory access controller to move the graphics request from the computer memory into the first processor'"'"'s input queue;

d. setting a flag if the input queue has insufficient space to hold the graphics request;

c. waiting for sufficient space in the input queue to hold the graphics request;

f. moving the graphics request from the computer memory into the first processor'"'"'s input queue; and

g. passing the token to the second processor'"'"'s input, the first and second processor being in a peer-to-peer configuration.

12. A graphics processing accelerator comprising:

a. a plurality of digital signal processors, each processor having an input in communication with a request bus and an output, the digital signal processors being arranged in a peer-to-peer configuration so as to process on a cyclical basis each successive graphics request available on a request bus; and

b. a sequencer in communication with each digital signal processor output for ordering graphics requests processed by the digital signal processors;

each digital signal processor further including;

an input manager processor for processing tasks defined by data on the token input, such tasks defined by a request type, coordinate data, attribute data, and a global request for all processors;

a renderer processor for processing the local request according to the request type into a processed request;

an executive processor for dispatching the local graphics request from the processor'"'"'s input to the renderer; and

an output manager processor for outputting processed graphics requests to the sequencer.

13. The system as defined by claim 12 wherein the executive processor further includes a clipping processor and a filtering processor, wherein the executive clips and filters the graphics request before dispatching the request to the renderer.

14. A graphics accelerator comprising:

a plurality of digital signal processors, each processor having an input in communication with a request bus and an output, the digital signal processors being arranged in a peer-to-peer configuration so as to process on a cyclical basis each successive graphics request available on a request bus; and

a sequencer in communication with each digital signal processor output for ordering graphics requests processed by the digital signal processors, wherein each digital signal processor further includes an input manager processor for processing tasks defined by data on a token input, such processing tasks being defined by a request type, coordinate data, attribute data, and a global request to all processors.

15. A graphics accelerator according to claim 14 wherein each digital signal processor further includes an output manager processor for outputting processed graphics requests to the sequencer.

16. The graphics accelerator as defined by claim 14 further comprising:

a distinct communication bus between the sequencer and each of the plurality of digital signal processors so that the sequencer can simultaneously receive a processed graphics request from each of the digital signal processors.

17. A graphics accelerator according to claim 14 wherein:

each of the digital signal processors includes a token input and a token output, the token output of a first one of the digital signal processors being coupled to the token input of a second one of the digital signal processors; and

the presence of a control token in the token input of a digital signal processor identifies an active digital signal processor and triggers the processing by such digital signal processor of a graphics request on the request bus, and after processing by such digital signal processor, the control token is provided upon the token output so that processing by all of the digital signal processors is controlled at a peer-to-peer level.

18. The graphics accelerator as defined by claim 17 wherein a token further includes an identifier of the digital signal processor placing the token upon the token output so that a first processor can determine when the token has traveled cyclically to all digital signal processors.

19. The graphics accelerator as defined by claim 17 wherein a digital signal processor receiving the control token can provide a skip token to the token output so that the processor may skip its having to process the graphics request on the request bus.

20. A graphics accelerator comprising:

a plurality of digital signal processors, each processor having an input in communication with a request bus and an output, the digital signal processors being arranged in a peer-to-peer configuration so as to process on a cyclical basis each successive graphics request available on a request bus; and

a sequencer in communication with each digital signal processor output for ordering graphics requests processed by the digital signal processors, wherein each digital signal processor further includes an output manager processor for outputting processed graphics requests to the sequencer.

21. The graphics accelerator as defined by claim 20 further comprising:

a distinct communication bus between the sequencer and each of the plurality of digital signal processors so that the sequencer can simultaneously receive a processed graphics request from each of the digital signal processors.

22. A graphics accelerator according to claim 20 wherein:

each of the digital signal processors includes a token input and a token output, the token output of a first one of the digital signal processors being coupled to the token input of a second one of the digital signal processors; and

the presence of a control token in the token input of a digital signal processor identifies an active digital signal processor and triggers the processing by such digital signal processor of a graphics request on the request bus, and after processing by such digital signal processor, the control token is provided upon the token output so that processing by all of the digital signal processors is controlled at a peer-to-peer level.

23. The graphics accelerator as defined by claim 22 wherein a token further includes an identifier of the digital signal processor placing the token upon the token output so that a first processor can determine when the token has traveled cyclically to all digital signal processors.

24. The graphics accelerator as defined by claim 22 wherein a digital signal processor receiving the control token can provide a skip token to the token output so that the processor may skip its having to process the graphics request on the request bus.

25. The graphics accelerator as defined by claim 20 wherein each digital signal processor further includes an input manager processor for processing tasks defined by data input.

26. The graphics accelerator as defined by claim 25 wherein the processing tasks are defined by a request type, coordinate data, attribute data, and a global request to all processors.