Cell plate structure for a ferroelectric memory
First Claim
Patent Images
1. A memory device comprising:
- an array of ferroelectric memory cells arranged in rows and columns, the memory cells having a first plate and a second plate;
a plurality of plate line segments corresponding to each row of the array, the plate line segments coupled to the second plate of the memory cells; and
a plurality of plate line driver circuits coupled to each one of the plate line segments, wherein the plurality of plate line driver circuits are located at opposite ends of each one of the plurality of plate line segments.
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Abstract
A ferroelectric memory is described which has a memory array arranged in rows and columns. The memory array includes a plate line which is segmented into sub-plate lines which correspond to a row of the memory. The plate line segments have multiple driver circuits coupled thereto for providing a plate line voltage signal. The memory array can include a global plate line coupled to the segments of the segmented plate line via an access switch, or transistor. A global plate line voltage is controlled by multiple plate line driver circuits.
105 Citations
19 Claims
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1. A memory device comprising:
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an array of ferroelectric memory cells arranged in rows and columns, the memory cells having a first plate and a second plate; a plurality of plate line segments corresponding to each row of the array, the plate line segments coupled to the second plate of the memory cells; and a plurality of plate line driver circuits coupled to each one of the plate line segments, wherein the plurality of plate line driver circuits are located at opposite ends of each one of the plurality of plate line segments. - View Dependent Claims (2, 3, 4, 5)
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6. A memory device comprising:
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an array of ferroelectric memory cells arranged in rows defined by wordlines and columns defined by bit lines; the memory cells having a first plate coupled to a bit line through an access transistor, the access transistor having a gate couple to a wordline for selective activation; a plurality of cell plate segments corresponding to the wordlines, and coupled to a second plate of the memory cells; a global plate line coupled to the plurality of cell plate segments through coupling transistors; and a plurality of global plate line drivers coupled to the global plate line for providing plate line signals. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A method of operating a ferroelectric memory device, the method comprising the steps of:
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providing an activation signals on a wordline to couple a memory cell to a digitline; providing a plate line signal on a plurality of plate line segments corresponding to the wordline, the plate line signal being generated using a plurality of plate line driver circuits, wherein the plurality of plate line driver circuits comprise two plate line driver circuits per each one of the plurality of plate line segments; and reading data stored in the memory cell. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A processing system comprising:
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a microprocessor coupled to a ferroelectric memory; and the ferroelectric memory comprising; an array of ferroelectric memory cells arranged in rows and columns, the memory cells having a first plate and a second plate; a plurality of plate line segments corresponding to each row of the array, the plate line segments coupled to the second plate of the memory cells; and a plurality of plate line driver circuits coupled to each one of the plate line segments, wherein the plurality of plate line driver circuits are located at opposite ends of each one of the plurality of plate line segments.
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Specification