Data input circuit for eliminating idle cycles in a memory device

• US 5,917,772 A
• Filed: 09/16/1997
• Issued: 06/29/1999
• Est. Priority Date: 09/16/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pawlowski, J. Thomas
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US08/931,779
• Time in Patent Office: 651 Days
• Field of Search: 365/189.05, 365/193, 365/189.02, 365/189.11, 365/230.02, 365/235, 365/189.04, 365/230.06, 365/230.08, 395/375, 395/511
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches

Abstract

A data input circuit including a first input register, a second input register, and a write driver connected to the second input register. The first and second input registers are preferably series-connected. In the preferred embodiment, a multiplexer selectively connects one of the first and second input registers to the write driver. The input circuit may be embodied in a memory device and in memory systems.

Claims

1. A memory device, comprising:

a memory array;

an address circuit connected to said memory array;

a write circuit including first and second data input registers and connected to said memory array;

an read circuit connected to said memory array;

a control circuit connected to said address circuit, said write circuit, and said read circuit, said control circuit including a first input enable register, a second input enable register connected to said first input enable register and having an output terminal connected to both said first and second data input registers, a first read enable register, and a second read enable register connected to said first read enable register and having an output terminal connected to said read circuit.

2. The memory device of claim 1, wherein said output terminal of said second read register is connected to said read circuit through a logic gate.

7. The memory device of claim 1, wherein said byte write circuit includes:

a first byte write enable register having an input terminal for receiving the byte write signal and having an output terminal;

a second byte write register having an input terminal connected to the output terminal of said first byte write register, and having an output terminal; and

a third byte write register having an input terminal connected to the output terminal of said second byte write register and an output terminal connected to said write driver.

8. The memory device of claim 7, wherein said third byte write register is connected to said write driver through a logic gate.

3. A memory device, comprising:

a memory array;

an address circuit connected to said memory array;

a write circuit including first and second data input registers and connected to said memory array;

an read circuit connected to said memory array; and

a control circuit connected to said address circuit, said write circuit, and said read circuit, said control circuit including a first input enable register, a second input enable register connected to said first input enable register and having an output terminal connected to both said first and second data input registers, a first read enable register, a second read enable register connected to said first read enable register and having an output terminal connected to said read circuit, and an output bypass register connected to both said second input enable register and said first read enable register and connected to said read circuit.

4. The memory device of claim 3, wherein said output bypass register is connected to said read circuit through a logic gate.

5. A memory device, comprising:

a memory array;

an address circuit;

a write circuit including first and second input registers and a write driver connected to said memory array;

a read circuit connected to said memory array;

a control circuit connected to said address circuit, said write circuit, and said read circuit, said control circuit including a first input enable register, a second input enable register connected to said first input enable register and having an output terminal connected to both said first and second data input registers, a first read enable register, a second read enable register connected to said first read enable register and having an output terminal connected to said read circuit; and

a byte write circuit for receiving a byte write signal and connected to said write driver in said write circuit.

6. The memory device of claim 5, wherein said byte write circuit receives a plurality of write signals.

9. The memory device of claim 5, wherein said byte write circuit includes a plurality of write drivers.

10. A memory device, comprising:

a memory array;

an address circuit connected to said memory array;

a write circuit including first and second input registers and connected to said memory array;

a read circuit, including a sense amplifier connected to said memory array, a first multiplexer connected to said sense amplifier, an output register connected to said first multiplexer, a second multiplexer connected to said output register, and an output buffer connected to said second multiplexer; and

a control circuit connected to said address circuit, said write circuit, and said read circuit.

11. A memory device, comprising:

a memory array;

an address circuit connected to said memory array;

a write circuit including first and second input registers and connected to said memory array;

a read circuit, including a sense amplifier connected to said memory array, a first multiplexer having a first terminal connected to said sense amplifier, a second terminal connected to said write circuit, and an output terminal, an output register connected to the output terminal of said first multiplexer, a second multiplexer having a first input terminal connected to said output register, a second input terminal connected to said write circuit, and an output terminal, and an output buffer connected to the output terminal of said second multiplexer; and

a control circuit connected to said address circuit, said write circuit, and said read circuit.

12. A memory device comprising,

a memory array;

an address circuit connected to said memory array;

a write circuit including first and second data input registers and connected to said memory array;

a read circuit including a sense amplifier connected to said memory array, an output register connected to said sense amplifier through a multiplexer, and an output buffer connected to said output register; and

a control circuit connected to said address circuit, said write circuit, and said read circuit.

13. A memory device comprising,

a memory array;

an address circuit connected to said memory array;

a write circuit including first and second data input registers and connected to said memory array;

a read circuit including a sense amplifier connected to said memory array, an output register connected to said sense amplifier, and an output buffer connected to said output register through a multiplexer; and

a control circuit connected to said address circuit, said write circuit, and said read circuit.