ATM reassembly controller and method

• US 5,917,828 A
• Filed: 01/03/1997
• Issued: 06/29/1999
• Est. Priority Date: 01/03/1997
• Status: Expired due to Term

• Current Assignee: Teradata US, Inc. (Teradata Corporation)
• Original Assignee: NCR Corporation
• Inventors: Thompson, Derek Andrew
• Primary Examiner(s): Hofsass, Jeffery A.
• Assistant Examiner(s): PEREZ PINEIRO, RAFAEL A
• Application Number:
  US08/778,536
• Time in Patent Office: 907 Days
• Field of Search: 370/395, 370/474, 370/397, 370/392, 370/471
• US Class Current: 370/474
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An ATM reassembly controller is disclosed that optimizes the utilization of host memory space and hardware resources such as I/O bus bandwidth, host memory bandwidth, memory system bandwidth and CPU resources. The system combines, whenever possible, the PDU status, PDU data and pointers to the host memory data buffers into a large burst write to the status queue. In addition, multiple status bundles are packed into a host memory buffer for efficient use of memory. An additional benefit of combining and packing information is that CPU resources are conserved by having combined the information the CPU must access into to a contiguous memory area.

Claims

1. An ATM reassembly controller for reassembling ATM cells into protocol data units for storage in main memory having main memory buffers and reassembly descriptor lists, comprising:

an input port for receiving an ATM cell;

a processor, operatively coupled to the input port, for identifying a virtual channel for the ATM cell, stripping a payload from the ATM cell associated with the identified virtual channel, and building a protocol data unit descriptor header for a reassembled protocol data unit constructed with the payload from the ATM cell;

a local memory buffer, coupled to the processor, for storing the payload and protocol data unit descriptor header;

a memory manager, operatively coupled to the processor, for assigning pointers to the local memory buffer and determining when the local memory buffer is full; and

a memory access controller, operatively coupled to the local memory buffer, for writing the content of the local memory buffer in a single burst to host memory for accessing by an application in response to determining that the local memory buffer is full.

2. The ATM reassembly controller of claim 1 further comprising a virtual channel indicator for indicating the state of the virtual channel.

3. The ATM reassembly controller of claim 1 further comprising:

a pointer controller for placing a main memory buffer pointer at the tail of the reassembly descriptor list in main memory;

a last cell indicator for indicating whether the cell is the last cell in the protocol data unit; and

second writing means for writing a PDU descriptor header to the reassembly descriptor list in response to determining that the cell is the last cell in the protocol data unit.

4. The ATM reassembly controller of claim 1 wherein the virtual channel indicator further comprises an activity indicator for determining whether the controller is receiving or idle.

5. The ATM reassembly controller of claim 4 wherein the activity indicator further comprises a first identifier for identifying the received cell as a first cell in response to determining that the virtual channel is idle.

6. The ATM reassembly controller of claim 4 wherein the activity indicator further comprises a second indicator for identifying the received cell as a last cell in response to reading a bit in the cell.

7. The ATM reassembly controller of claim 1 further comprising a local memory buffer allocator for assigning a local memory buffer pointer for a new local memory buffer.

8. The ATM reassembly controller of claim 7 further comprising a reassembly connection table entry having a reassembly address field for placing of the pointer, the placing of the pointer changing the state of the virtual channel from idle to receiving.

9. The ATM reassembly controller of claim 1 wherein the memory access controller further comprises a capacity indicator for determining whether all of the payload will fit in the local memory buffer.

10. An ATM reassembly controller, comprising:

an input port for receiving a cell;

a register, operatively coupled to the input port, for determining a virtual channel associated with the received cell;

a local memory buffer allocator, coupled to the register, for allocating a local memory buffer and for storing in the local memory buffer a payload stripped from the received cell;

a main memory buffer allocator, operatively coupled to the local memory buffer allocator for allocating a main memory buffer; and

a memory access controller, coupled to the local memory buffer, for writing the contents of the local memory buffer into the main memory buffer in a single burst write operation.

11. The ATM reassembly controller of claim 10 further comprising an indicator for indicating a state for the virtual channel.

12. The ATM reassembly controller of claim 10 further comprising:

a reassembly descriptor list for storing a main memory buffer pointer; and

a first identifier for identifying whether the cell is the last cell in a protocol data unit;

wherein the memory access controller writes a PDU descriptor header to the reassembly descriptor list in response to determining that the cell is the last cell in a protocol data unit.

13. The ATM reassembly controller of claim 11 wherein the indicator for indicating the state of the virtual channel further comprises an activity indicator for determining whether the controller is receiving or idle.

14. The ATM reassembly controller of claim 13 wherein the activity indicator further comprises a second identifier for identifying the received cell as a first cell in response to determining that the state of the virtual channel is idle.

15. The ATM reassembly controller of claim 13 wherein the first identifier identifies the received cell as a last cell by reading a bit in the cell.

16. The ATM reassembly controller of claim 10 wherein the local memory buffer allocator further comprises a pointer register for assigning a local memory buffer pointer for the local memory buffer.

17. The ATM reassembly controller of claim 16 wherein the local memory buffer allocator further comprises a reassembly connection table entry having a reassembly address field for placing the pointer, the placing of the pointer changing the state of the virtual channel from idle to receiving.

18. The ATM reassembly controller of claim 10 wherein the memory access controller further comprises a capacity indicator for indicating whether all of the payload will fit in the local memory buffer.

19. A method of reassembling ATM cells, comprising the steps of:

receiving a cell;

determining a virtual channel number associated with the received cell;

determining the state of the virtual channel;

allocating a local memory buffer for storing a payload stripped from the received cell associated with the virtual channel;

storing the payload in a local memory buffer;

allocating a main memory buffer; and

writing the contents of the local memory buffer into the main memory buffer in a single burst write operation.

20. The method of claim 19 further comprising the steps of:

placing a main memory buffer pointer at the tail of a reassembly descriptor list;

determining whether the cell is the last cell in a protocol data unit; and

writing a PDU descriptor header to the reassembly descriptor list in response to determining that the cell is the last cell in a protocol data unit.

21. The method of claim 19 wherein the step of determining the state of the virtual channel further comprises the step of determining whether the controller is receiving or idle.

22. The method of claim 21 wherein the step of determining whether the controller is receiving or idle further comprises the step of identifying the received cell as a first cell in response to determining that the state of the virtual channel is idle.

23. The method of claim 21 wherein the step of determining whether the controller is receiving or idle further comprises the step of identifying the received cell as a last cell in response to reading a bit in the cell.

24. The ATM reassembly controller of claim 19 wherein the step of allocating a local memory buffer further comprises the step of assigning a local memory buffer pointer for the local memory buffer.

25. The method of claim 24 wherein the step of allocating a local memory buffer further comprises the step of placing the pointer into a local memory reassembly address field of a reassembly connection table entry, the placing of the pointer changing the state of the virtual channel from idle to receiving.

26. The method of claim 19 wherein the step of writing further comprises the step of determining whether all of the payload will fit in the local memory buffer.

27. The method of claim 26 wherein the step of determining whether all of the payload will fit in the local memory buffer occurs before the payload is stored in the local memory buffer.