Bit synchronization circuit and method capable of correct bit synchronization for both 2-value and 4-value FSK transmission signals

• US 5,917,871 A
• Filed: 01/30/1997
• Issued: 06/29/1999
• Est. Priority Date: 02/15/1996
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamaki, Yoichi
• Primary Examiner(s): Bocure, Tesfaldet
• Assistant Examiner(s): WEBSTER, BRYAN E
• Application Number:
  US08/791,825
• Time in Patent Office: 880 Days
• Field of Search: 375/316, 375/334, 375/354, 375/335, 375/362, 375/364, 340/825.44, 329/300-303
• US Class Current: 375/364
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: H04W 52/0283 with sequential power up or power down of successive circuit blocks, e.g. switching on the local oscillator before RF or mixer stages
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A bit synchronization circuit receives polarity-judged output signal and a level-judged output signal that are produced through demodulation of a 2-value FSK or 4-value FSK transmission signal. Flip-flop circuits and an exclusive-OR circuit generate a second sampling output by sampling and delaying the polarity-judged output signal. Flip-flop circuits and an exclusive-NOR circuit generate a third sampling signal having a given temporal relationship with the second sampling output by sampling and delaying the level-judged output signal. AND circuits supply a correction signal to a counter circuit when levels of the second and third sampling outputs and a phase signal indicating a correction period of the counter circuit satisfy a given relationship. In response to the correction signal, the counter circuit corrects its count so as to produce a clock signal having a rate that is equal to a transmission rate of the transmission signal.

Claims

1. A bit synchronization method comprising the steps of:

receiving a polarity-judged output signal obtained by detecting polarity variations of a demodulation signal obtained by demodulating a transmission signal that is modulated according to 2-value FSK or 4-value FSK and a level-judged output signal obtained by detecting level variations of the demodulating signal;

generating a first sampling output by sampling and delaying a state variation of the polarity-judged output signal with a sampling signal;

generating a phase signal indicating a period during which a count of a counter circuit needs to be corrected;

generating, when levels of the first sampling output and the phase signal satisfy a given relationship, a correction signal indicating that the count of the counter circuit should be corrected; and

in response to the correction signal, adding to or subtracting from the count of the counter circuit a number corresponding to an integral multiple of a reference clock period so that a clock signal that is output from the counter circuit has a rate equal to a transmission rate of the transmission signal.

2. A bit synchronization method comprising the steps of:

receiving a polarity-judged output signal obtained by detecting polarity variations of a demodulation signal obtained by demodulating a transmission signal that is modulated according to 2-value FSK or 4-value FSK and a level-judged output signal obtained by detecting level variations of the demodulating signal;

generating a first sampling output by sampling and delaying a state variation of the polarity-judged output signal;

generating a phase signal indicating a period during which a count of a counter circuit needs to be corrected;

generating, when levels of the first sampling output and the phase signal satisfy a given relationship, a correction signal indicating that the count of the counter circuit should be corrected; and

in response to the correction signal, adding to or subtracting from the count of the counter circuit a number corresponding to an integral multiple of a reference clock period so that a clock signal that is output from the counter circuit has a rate equal to a transmission rate of the transmission signal;

wherein the phase signal includes an on-period during which the count of the counter circuit needs to be increased and an off-period during which the count of the counter circuit needs to be decreased, and wherein an addition correction signal is generated when the first sampling output turns on in the on-period of the phase signal, and a substraction correction signal is generated when the first sampling output turns on in the off-period of the phase signal.

3. A bit synchronization method comprising the steps of:

receiving a polarity-judged output signal obtained by detecting polarity variations of a demodulation signal obtained by demodulating a transmission signal that is modulated according to 2-value FSK or 4-value FSK and a level-judged output signal obtained by detecting level variations of the demodulation signal;

generating a second sampling output by sampling and delaying a state variation of the polarity-judged output signal;

generating a third sampling output having a given temporal relationship with the second sampling output by sampling and delaying a state variation of the level-judged output signal;

generating a phase signal indicating a period during which a count of a counter circuit needs to be corrected;

generating, when levels of the second sampling output, the third sampling output, and the phase signal satisfy a given relationship, a correction signal indicating that the count of the counter circuit should be corrected; and

in response to the correction signal, adding to or subtracting from the count of the counter circuit a number corresponding to an integral multiple of a reference clock period so that a clock signal that is output from the counter circuit has a rate equal to a transmission rate of the transmission signal.

4. The bit synchronization method according to claim 3, wherein the given temporal relationship is such that the second sampling output is generated at a time point when a time corresponding to a half symbol length or a half bit length has elapsed from sampling of the state variation of the level-judged output signal, and that the third sampling output is generated at a time point when the time corresponding to the half symbol length or the half bit length has elapsed from generation of the second sampling output.

5. The bit synchronization method according to claim 3, wherein the third sampling output is turned on only when both of an output obtained by first sampling the state variation of the level-judged output signal and an output obtained by delaying the output obtained by first sampling the state variation of the level-judged output signal by a half symbol length or a half bit length are 1 or 0.

6. The bit synchronization method according to claim 3, wherein the phase signal indicates a period during which the count of the counter circuit needs to be increased and a period during which the count of the counting circuit needs to be decreased, and wherein an addition correction signal is generated if the phase signal is on when both of the second and third sampling outputs are on, and a subtraction correction signal is generated if the phase signal is off when both of the second and third sampling outputs are on.

7. The bit synchronization method according to claim 3, wherein if the third sampling output is off when the second sampling output turns on, the correction signal is prohibited from being output, to prevent an erroneous bit synchronization correction in the counter circuit.

8. The bit synchronization method according to claim 3, further comprising the steps of:

judging whether the transmission signal is a 2-value FSK transmission signal or a 4-value FSK transmission signal; and

disabling the level-judged output signal when the 2-value FSK transmission signal is received,

whereby the 2-value FSK transmission signal and the 4-value FSK transmission signal are selectively subjected to bit synchronization.

9. The bit synchronization method according to claim 8, wherein the phase signal indicates a period during which the count of the counter circuit needs to be increased and a period during which the count of the counting circuit needs to be decreased, and wherein an addition correction signal is generated if the phase signal is on when the second sampling output turns on, and a subtraction correction signal is generated if the phase signal is off when the second sampling output turns on.

10. A bit synchronization circuit which receives a polarity-judged output signal obtained by detecting polarity variations of a demodulation signal obtained by demodulating a transmission signal that is modulated according to 2-value FSK or 4-value FSK and a level-judged output signal obtained by detecting level variations of the demodulation signal, said bit synchronization circuit comprising:

means for generating a second sampling output by sampling and delaying a state variation of the polarity-judged output signal;

means for generating a third sampling output having a given temporal relationship with the second sampling output by sampling and delaying a state variation of the level-judged output signal;

a counter circuit for counting reference clocks to produce a clock signal;

means for generating a phase signal indicating a period during which a count of the counter circuit needs to be corrected;

means for generating, when levels of the second sampling output, the third sampling output, and the phase signal satisfy a given relationship, a correction signal indicating that the count of the counter circuit should be corrected; and

means, responsive to the correction signal, for adding to or subtracting from the count of the counter circuit a number corresponding to an integral multiple of a period of the reference clocks so that the clock signal has a rate equal to a transmission rate of the transmission signal.

11. The bit synchronization circuit according to claim 10, wherein the means for generating the second sampling output includes plural stages of flip-flop circuits and an exclusive-OR circuit, and the means for generating the third sampling output includes plural stages of flip-flop circuits and an exclusive-NOR circuit.

12. The bit synchronization circuit according to claim 10, wherein the means for generating the correction signal does not generate the correction signal if the third sampling output is off when the second sampling output turns on, to prevent an erroneous bit synchronization correction with the counter circuit.

13. The bit synchronization circuit according to claim 10, further comprising:

means for judging whether the transmission signal is a 2-value FSK transmission signal or a 4-value FSK transmission signal; and

means for disabling the level-judged output signal when the 2-value FSK transmission signal is received,

whereby the 2-value FSK transmission signal and the 4-value FSK transmission signal are selectively subjected to bit synchronization.

14. A selective calling receiver comprising:

an antenna for receiving a transmission signal modulated according to 2-value FSK or 4-value FSK;

a demodulation section for demodulating the received transmission signal to produce a demodulation signal;

a decoder for decoding the demodulation signal to extract transmission data, the decoder including the bit synchronization circuit according to claim 10;

a memory element for storing a calling number of the selective calling receiver;

a display device for displaying necessary information;

a speaker for generating a singing for calling notification; and

a CPU for controlling the demodulation section, the decoder, the memory element, and the display device.