Receiving apparatus, receiving method, and digital PLL circuit

• US 5,917,873 A
• Filed: 10/06/1997
• Issued: 06/29/1999
• Est. Priority Date: 10/08/1996
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yuchi, Hirofumi, Shiomoto, Shoji
• Primary Examiner(s): Ghebretinsae, Temesghen
• Application Number:
  US08/944,849
• Time in Patent Office: 631 Days
• Field of Search: 375/374, 375/376, 375/294, 327/156, 327/160, 327/147, 331/DIG. 2
• US Class Current: 375/376
• CPC Class Codes: H03L 7/107 using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H04B 7/18523 Satellite systems for providing broadcast service to terrestrial stations, i.e. broadcast satellite service arrangements specially adapted for satellite broadcast receiving H04H40/90; picture transmission via satellite H04N1/00103; television transmission via satellite H04N7/20
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04N 21/4221 Dedicated function buttons, e.g. for the control of an EPG, subtitles, aspect ratio, picture-in-picture or teletext
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4332 by placing content in organized collections, e.g. local EPG data repository interfaces, Database management systems or updating for information retrieval G06F16/23; details of retrieval of video data and associated meta data in video database G06F16/739
• CPC Class Codes: H04N 21/4382 Demodulation or channel decoding, e.g. QPSK demodulation analog front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 21/4405 involving video stream decryption
• CPC Class Codes: H04N 21/482 End-user interface for program selection broadcast systems using EPGs H04H60/72
• CPC Class Codes: H04N 21/6143 involving transmission via a satellite

Abstract

A PCR is detected from a bit stream by a PCR extracting circuit. When the time reference value is detected, an STC counter counts a clock oscillated by a VCO and compares the value of the STC counter and the value of the PCR. The phase difference is fed back to the VCO through a digital filter. In the control start stage, the gain of the digital filter is designated to a large value. Thus, the phase difference is quickly converged to the allowable difference range. In the lock stage, the gain is designated to a small value. Thus, the control operation is stably performed. In the nearly unlock stage, the gain is designated to a middle value. Thus, the phase difference is quickly pulled to the allowable difference range.

Claims

1. A receiving apparatus having a digital PLL circuit for generating a system clock corresponding to time reference information sent along with data and data process means for processing the data corresponding to the system clock,

the PLL circuit comprising:

time reference information detecting means for detecting time reference information from the data and outputting the time reference information;

variable frequency generating means for generating a clock with a predetermined frequency;

clock count number outputting means for counting the clock and outputting the counted result;

phase comparing means for comparing the time reference information and the counted result at a timing of which the time reference information is detected; and

a feedback loop for feeding back the phase difference as a control signal to said variable frequency generating means through a filter means,

wherein said filter means is coupled to the phase comparing means and includes calculating means for performing a predetermined calculation on received inputs and arithmetic means for performing an arithmetic operation on an output of the calculating means in accordance with a variable factor which varies in accordance with the received inputs of said calculating means.

2. The receiving apparatus as set forth in claim 1,

wherein the PLL circuit has at least a first loop gain used in a control beginning state and a second loop gain used in other than the control beginning state, the first loop gain being larger than the second loop gain.

3. The receiving apparatus as set forth in claim 1,

wherein the filter means has detecting means for detecting whether the phase difference is within a predetermined phase difference, and

wherein a first loop gain in the case that the phase difference is within the predetermined phase difference is smaller than a second loop gain in the case that the phase difference is not within the predetermined phase difference.

4. The receiving apparatus as set forth in claim 1, wherein the arithmetic means includes a multiplying device and wherein the multiplying device multiplies the output of said calculating means by the variable factor.

5. A receiving apparatus having a digital PLL circuit for generating a system clock corresponding to time reference information sent along with data and data process means for processing the data corresponding to the system clock,

the PLL circuit comprising:

time reference information detecting means for detecting time reference information from the data and outputting the time reference information;

variable frequency generating means for generating a clock with a predetermined frequency;

clock count number outputting means for counting the clock and outputting the counted result;

phase comparing means for comparing the time reference information and the counted result at a timing of which the time reference information is detected; and

a feedback loop for feeding back the phase different as a control signal to said variable frequency generating means through a filter means,

wherein a designated state of the filter means is varied corresponding to the phase difference,

wherein the filter means has detecting means for detecting whether the phase difference is within a predetermined phase difference,

wherein a first loop gain in the case that the phase difference is smaller than a second loop gain in the case that the phase difference is not within the predetermined phase difference,

wherein the detecting means further determines whether or not the difference between a first phase difference detected at first timing and a second phase difference detected at a second timing immediately preceding the first timing immediately preceding the first timing is within a predetermined difference, and

wherein a loop gain of the filter means is designated to the first loop gain when the difference is within the predetermined difference and when the phase difference is within the predetermined phase difference.

6. A receiving apparatus having a digital PLL circuit for generating a system clock corresponding to time reference information sent along with data and data process means for processing the data corresponding to the system clock,

the PLL circuit comprising:

time reference information detecting means for detecting time reference information from the data and outputting the time reference information;

variable frequency generating means for generating a clock with a predetermined frequency;

clock count number outputting means for counting the clock and outputting the counted result;

phase comparing means for comparing the time reference information and the counted result at a timing of which the time reference information is detected; and

a feedback loop for feeding back the phase different as a control signal to said variable frequency generating means through a filter means,

wherein a designated state of the filter means is varied corresponding to the phase difference, and

wherein the PLL circuit divides the difference between a first phase difference detected at a first timing and a second phase difference detected at a second timing immediately preceding the first timing phase by a value corresponding to an interval between the first timing and the second timing, multiplies the divided result by a predetermined coefficient K, adds the multiplied result and a control value detected at the second timing, and obtains the added result as a control value of the first timing.

7. The receiving apparatus as set forth in claim 6,

wherein the PLL circuit varies the coefficient K so as to vary the designated state.

8. A receiving method for use with a receiving apparatus having a digital PLL circuit for generating a system clock corresponding to time reference information sent along with data and data process means for processing the data corresponding to the system clock, the method comprising the steps of:

detecting time reference information from the data and outputting the time reference information;

generating a clock with a predetermined frequency;

counting the clock and outputting the counted result;

comparing the time reference information and the counted result at a timing of which the time reference information is detected;

feeding back through a filter means the phase difference as a control signal to control the clock; and

varying a variable factor of the filter means,

wherein the filter means includes calculating means for performing a predetermined calculation on received inputs and arithmetic means for performing an arithmetic operation on an output of the calculating means in accordance with a variable factor which varies in accordance with the received inputs of said calculating means.

9. The receiving method as set forth in claim 8, further comprising the step of:

multiplying the output of said calculating means by the variable factor.

10. A digital PLL circuit for generating a system clock corresponding to time reference information sent along with data, comprising:

time reference information detecting means for detecting time reference information from the data and outputting the time reference information;

variable frequency generating means for generating a clock with a predetermined frequency;

clock count number outputting means for counting the clock and outputting the counted result;

phase comparing means for comparing the time reference information and the counted result at a timing of which the time reference information is detected; and

a feedback loop for feeding back the phase difference as a control signal to said variable frequency generating means through a filter means,

wherein said filter means is coupled to the phase comparing means and includes calculating means for performing a predetermined calculation on received inputs and arithmetic means for performing an arithmetic operation on an output of the calculating means in accordance with a variable factor which varies in accordance with the received inputs of said calculating means.

11. The receiving apparatus as set forth in claim 10, wherein the arithmetic means includes a multiplying device and wherein the multiplying device multiplies the output of said calculating means by the variable factor.