Semiconductor optical waveguide

• US 5,917,981 A
• Filed: 05/13/1998
• Issued: 06/29/1999
• Est. Priority Date: 02/29/1996
• Status: Expired due to Fees

• Current Assignee: Rockstar Consortium US LP (Rockstar Consortium Inc.)
• Original Assignee: Northern Telecom Limited (Nortel Networks Corporation)
• Inventors: Ojha, Jugnu J., Kovacic, Stephen J.
• Primary Examiner(s): Ullah, Akm E.
• Application Number:
  US09/076,320
• Time in Patent Office: 412 Days
• Field of Search: 385/131, 385/4, 385/129-132, 385/2, 385/14, 385/33, 385/35, 385/49, 385/89, 385/93, 385/96, 427/571, 427/573, 427/575, 359/248, 438/39, 438/180, 438/571, 438/969, 438/71, 438/97, 438/25, 438/27, 438/492, 65/36, 372/45, 372/50, 257/432, 257/433, 257/22, 257/17, 257/18, 257/19, 257/184, 257/185, 437/19, 437/22, 437/110, 437/133, 437/147, 437/167, 437/936, 437/24, 437/129
• US Class Current: 385/131
• CPC Class Codes: G02B 2006/12061 Silicon
• CPC Class Codes: G02B 6/10 of the optical waveguide type G02B6/02, G02B6/24 take precedence; devices or arrangements for the control of light by electric, magnetic, electro-magnetic or acoustic means G02F1/00; transferring the modulation of modulated light G02F2/00; optical logic elements G02F3/00; optical analogue/digital converters G02F7/00
• CPC Class Codes: G02B 6/12004 Combinations of two or more optical elements
• CPC Class Codes: G02B 6/122 Basic optical elements, e.g. light-guiding paths
• CPC Class Codes: H01L 31/02327 the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: H01L 31/1812 including only AIVBIV alloys, e.g. SiGe
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

A channel waveguide structure which can be incorporated into VLSI (very large scale integration) integrated circuits uses a SiGe (silicon germanium) alloy core and Si (silicon) top and bottom cladding layers. The core may consist of only a SiGe alloy layer or it may be formed as a superlattice containing Si layers alternating with SiGe alloy layers. LOCOS (locally oxidized silicon) regions are formed on the top cladding layer at spaced locations thereby defining lateral boundaries of channels in the core.

Claims

1. A method of making an optoelectronic integrated circuit comprising the steps of:

forming on a silicon substrate a first layer of silicon including buried regions of n+ or p+ doping;

growing a second layer of silicon over the first layer;

growing a core comprising at least one layer of a silicon alloy;

growing a third layer of silicon over the core layer;

depositing LOCOS protect layers of polysilicon and silicon nitride;

patterning and etching the LOCOS protect layers thereby creating exposed regions on the third layer of silicon;

growing oxide in the exposed regions; and

removing the LOCOS protect layers.

12. A method according to claim 1 adapted to result in the formation of a P-i-N photodetector diode, the method further comprising the steps of:

making a region of n+doping in the substrate or in the first layer;

growing the second layer, the core and the third layer such that they are n-doped;

growing a p+doped layer of silicon overlying said third layer above said buried n+doped region on an area on which oxide has not been grown.

13. A method according to claim 1 adapted to result in the formation of a N-i-P photodetector diode, the method further comprising the steps of:

making a region of p+doping in the substrate or in the first layer;

growing the second layer, the core and the third layer such that they are p-doped;

growing a n+doped layer of silicon overlying said third layer above said buried p+doped region on an area on which oxide has not been grown.

2. A method of making an optoelectronic integrated circuit comprising the steps of:

forming on a silicon substrate a first layer of silicon including buried regions of n+ or p+ doping;

growing a second layer of silicon over the first layer;

growing a core comprised of at least one layer made of a silicon alloy;

growing a third layer of silicon over the core layer;

depositing trench protect layers;

patterning and etching the trench regions; and

filling the trenches with a material, the material having an index of refraction less than that of the cladding in the case the trenches do not penetrate the core, the material having an index of refraction less than that of the core in the case the trenches do penetrate the core.

3. A method of making an optoelectronic integrated circuit comprising the steps of:

growing on a substrate a first layer of silicon;

growing a core comprising at least one layer of a silicon alloy;

growing a second layer of silicon over the core layer;

depositing LOCOS protect layers of polysilicon and silicon nitride;

patterning and etching the LOCOS protect layers thereby creating exposed regions on the third layer of silicon;

growing oxide in the exposed regions; and

removing the LOCOS protect layers.

4. A method according to claim 3 wherein the core has a predetermined increase in the index of refraction relative to the first and second layers.

5. A method according to claim 4 wherein the layers within the core are grown such that they comprise a crystal which is substantially free of dislocations.

6. A method according to claim 4 wherein the core is formed of a single layer of a silicon semiconductor alloy.

7. A method according to claim 3 wherein said step of growing the core comprises growing a series of layers each of which is silicon or a silicon alloy.

8. A method according to claim 7 wherein the series of layers comprise layers of silicon alternating with layers of silicon alloy.

9. A method according to claim 8 wherein the series of layers comprise a superlattice.

10. A method according to claim 8 wherein the series of layers comprise a multiple quantum well.

11. A method according to claim 6 wherein the silicon alloy is Si_1-x Ge_x where x is in the range 0.01-0.1, and where x is selected to provide said predetermined increase in the index of refraction in the core.

14. A method of making an optoelectronic integrated circuit comprising the steps of:

forming on a silicon substrate a first layer of silicon;

growing a second layer of silicon over the first layer;

growing a core comprised of at least one layer made of a silicon alloy;

growing a third layer of silicon over the core layer;

depositing trench protect layers;

patterning and etching the trench regions; and

filling the trenches with a material, the material having an index of refraction less than that of the third layer in the case the trenches do not penetrate the core, the material having an index of refraction less than that of the core in the case the trenches do penetrate the core.

15. A method according to claim 14 wherein the core is grown to have a predetermined increase in the index of refraction relative to the second and third layers.

16. A method according to claim 15 wherein the layers within the core are grown to comprise a crystal which is substantially free of dislocations.

17. A method according to claim 15 wherein the trench regions extend through the bottom cladding layer to the substrate.

18. A method according to claim 15 wherein the core is formed of a single layer of a silicon semiconductor alloy.

19. A method according to claim 15 wherein the core comprises a series of layers each of which is silicon or a silicon alloy.

20. A method according to claim 19 wherein the series of layers comprise layers of silicon alternating with layers of silicon alloy.

21. A method according to claim 19 wherein the series of layers comprise a superlattice.

22. A method according to claim 19 wherein the series of layers comprise a multiple quantum well.

23. A method according to claim 15 wherein the silicon alloy is Si_1-x Ge_x where x is in the range 0.01-0.1, and where x is selected to provide said predetermined increase in the index of refraction in the core.

24. A method according to claim 15 adapted to result in the formation of a P-i-N photodetector diode, the method further comprising the steps of:

making a region of n+doping in the substrate or in the first layer;

growing the second layer, the core and the third layer such that they are n-doped;

growing a p+doped layer of silicon overlying said third layer above said buried n+doped region on an area in which trench regions were not formed.

25. A method according to claim 15 adapted to result in the formation of a N-i-P photodetector diode, the method further comprising the steps of:

making a region of p+doping in the substrate or in the first layer;

growing the second layer, the core and the third layer such that they are p-doped;

growing a n+doped layer of silicon overlying said third layer above said buried p+doped region on an area in which trench regions were werenot formed.

26. A method according to claim 14 further comprising the step of filling the trench regions with silicon dioxide.

27. A method according to claim 14 further comprising the steps of forming a silicon liner on each trench region and filling it with polysilicon.

28. A method according to claim 14 further comprising the step of filling the trench regions with a polymer.