Apparatus and method for smart host bus adapter for personal computer cards

• US 5,918,028 A
• Filed: 07/08/1997
• Issued: 06/29/1999
• Est. Priority Date: 07/08/1997
• Status: Expired due to Fees

• Current Assignee: General Dynamics C4 Systems Incorporated (General Dynamics Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Anderson, Jack Lee, Silverthorn, Lee
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US08/889,726
• Time in Patent Office: 721 Days
• Field of Search: 395/281-283, 395/309, 395/284, 395/285, 395/830, 395/833, 395/842, 395/847, 395/853, 395/857, 395/858, 395/868, 395/883, 395/735, 395/741, 395/742
• US Class Current: 710/306
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438

Abstract

A system is shown to improve data transfer between computers and PC Cards, which have a Host Bus Adapter (HBA). Previous HBA designs are limited in routing interrupts to the system and transferring data. The Smart HBA (150) detects an interrupt, alerts a target controller of the interrupt and provides a vector to the PC Card driver. This also eliminates acknowledgment routines and saves bus cycles. To each PC Card it appears that it is interfacing directly to its software driver. The command handling feature allows bus agents to communicate between fast access devices without using Peripheral Component Interconnect (PCI) commands that cannot be posted. Thus all commands can be posted in PCI bridges, no bus accesses have to wait for arbitration across multiple busses and no slow devices require a retry. Direct memory access (DMA) operations can be performed by legacy PC Cards when connected to a PCI bus.

Claims

1. An apparatus for a Smart Host Bus Adapter (HBA) for seamlessly interfacing computer cards with computers, said apparatus comprising:

a plurality of channel devices, each channel device including;

a single port for connecting to a peripheral component interconnect (PCI) bus;

an interrupt handler coupled to said single port;

a direct memory access controller (DMAC) device coupled to said single port;

a state machine operable to;

decode and execute a set of commands as received from a controller;

initiate commands and alert or acknowledgment messages to agents on a peripheral component interconnect (PCI) bus

perform a direct memory access controller (DMAC) function, said state machine coupled to said single port;

said direct memory access controller (DMAC) device is coupled to each channel device of said plurality of channel devices for controlling memory access by said computer cards; and

each of said plurality of channel devices further includes an interrupt vector register coupled to a channel device to provide a vector for interrupts.

2. An apparatus for a Smart Host Bus Adapter (HBA) for computer cards as claimed in claim 1, wherein each channel device includes said state machine for generating a command upon detection of an interrupt.

3. An apparatus for a Smart Host Bus Adapter (HBA) for computer cards as claimed in claim 1, wherein each of said plurality of channel devices further includes a starting address register coupled to a channel device to provide a starting address.

4. An apparatus for a Smart Host Bus Adapter (HBA) for computer cards as claimed in claim 1, wherein each of said plurality of channel devices further includes a target controller address register coupled to a channel device to provide an address for a target controller to store data.

5. An apparatus for a Smart Host Bus Adapter (HBA) for computer cards as claimed in claim 1, wherein each of said plurality of channel devices further includes a burst length register coupled to a channel device for storing a length for a burst of data.

6. An apparatus for a Smart Host Bus Adapter (HBA) for computer cards as claimed in claim 1, wherein each of said plurality of channel devices further includes a First-In First-Out (FIFO) memory coupled to a channel device for storing data.

7. An apparatus for a Smart Host Bus Adapter (HBA) for computer cards as claimed in claim 1, wherein each of said plurality of channel devices further includes a data memory coupled to a channel device for storing data.

8. An apparatus for a Smart Host Bus Adapter (HBA) for computer cards as claimed in claim 1, wherein each of said plurality of channel devices further includes a mailbox address register coupled to a channel device to provide a mailbox address storage for a target controller.

9. An apparatus for a Smart Host Bus Adapter (HBA) for computer cards as claimed in claim 1, wherein each of said plurality of channel devices further includes a command handler, which includes:

a command register;

and said state machine for executing a command set.

10. An apparatus for a Smart Host Bus Adapter (HBA) for computer cards as claimed in claim 1, wherein each of said plurality of channel devices further includes data buffers coupled to a channel device, said data buffers accepting posted transactions as burst transfers from a peripheral component interconnect (PCI) bus.

11. An apparatus for a Smart Host Bus Adapter (HBA) for computer cards as claimed in claim 1, wherein each of said plurality of channel devices further includes a plurality of peripheral component interconnect (PCI) busses.

12. An apparatus for a Smart Host Bus Adapter (HBA) for computer cards as claimed in claim 6, wherein each of said plurality of channel devices further includes a direct memory access (DMA) length register coupled to the channel device for storing a length of memory data to be transferred during a direct memory access (DMA) operation.

13. An apparatus for a Smart Host Bus Adapter (HBA) for computer cards as claimed in claim 12, wherein said command register is located in a peripheral component interconnect (PCI) memory space, said command register coupled to said plurality of channel devices.

14. A method to improve functionality of computer cards in a computer system between a Smart Host Bus Adapter (HBA) and portable equipment, said method comprising the steps of:

generating commands upon detection of a computer interrupt;

decoding a set of commands received from a computer controller;

executing a set of commands received from a computer controller;

performing a direct memory access (DMA) control function on data; and

arbitrating between channels and peripheral component interconnect (PCI) busses.

15. A method to improve functionality of computer cards in a computer system between a Smart Host Bus Adapter (HBA) and portable equipment, as claimed in claim 14, wherein said generating commands step further includes a step of sending said set of commands during a data phase of a peripheral component interconnect (PCI) transaction.

16. A method to improve functionality of computer cards in a computer system between a Smart Host Bus Adapter (HBA) and portable equipment, as claimed in claim 14, wherein said method further includes a step of operating a plurality of channels simultaneously and independently of each other comprising the steps of:

generating commands upon detection of computer interrupts;

decoding said set of commands received from said computer controller to generate a set of decoded commands;

executing said set of decoded commands; and

performing said direct memory access (DMA) control function on data.

17. A method to improve functionality of computer cards in a computer system between a Smart Host Bus Adapter (HBA) and portable equipment, as claimed in claim 14, wherein there is further included a step of emptying a plurality of data buffers prior to performing said decoding step.