Data processing system having an input/output coprocessor with a separate visibility bus

• US 5,918,064 A
• Filed: 02/18/1997
• Issued: 06/29/1999
• Est. Priority Date: 02/18/1997
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Goler, Vernon Bernard, Miller, Gary Lynn
• Primary Examiner(s): Ramirez, Ellis B.
• Assistant Examiner(s): TITCOMB, WILLIAM D
• Application Number:
  US08/801,284
• Time in Patent Office: 861 Days
• Field of Search: 395/800.32, 395/800.34, 395/306, 395/309, 395/585, 395/800.38, 395/308
• US Class Current: 712/38
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Abstract

A data processing system includes a central processing unit (CPU) (20), a peripheral bus (32), and an input/output (I/O) coprocessor (38). The CPU (20) and the I/O coprocessor (38) are coupled to the peripheral bus (32). The I/O coprocessor (38) has a plurality of front-end channels (50) for receiving a time-base, and in response, for providing a time-base reference for input signals and generating output signals using the time-base reference. A back-end processor (80) controls operation of the plurality of front-end channels (50) in response to executing instructions. A visibility bus (40), coupled to the back-end processor (80), is for providing visibility of the internal registers of the back-end processor (80) independent of the CPU (20). The visibility is provided for development of the instructions executed by the back-end processor (80).

Claims

1. A data processing system, comprising:

a central processing unit for executing first instructions;

a peripheral bus, coupled to the central processing unit; and

an input/output coprocessor, coupled to the peripheral bus, the input/output coprocessor comprising

a plurality of front-end channels having a plurality of input/output terminals, the plurality of front-end channels for receiving a time-base value, and in response, for providing a time-base reference for input signals and for generating output signals using the time-base reference, wherein the time-base value is used by the plurality of front-end channels to implement a timer function;

a back-end processor, coupled to the plurality of front-end channels, for controlling operation of the plurality of front-end channels in response to executing second instructions, wherein the second instructions are different than the first instructions;

a visibility bus, coupled to the back-end processor, for providing visibility of internal registers of the back-end processor for development of the second instructions, wherein the visibility is provided independent of the central processing unit; and

a storage unit, coupled to the back-end processor, for storing the second instructions.

2. The data processing system of claim 1, further comprising a second input/output coprocessor, coupled to the peripheral bus and to the visibility bus.

3. The data processing system of claim 1, further comprising:

a multiplexer having a first plurality of input/output terminals coupled to the plurality of input/output terminals of the plurality of front-end channels, a second plurality of input/output terminals coupled to the visibility bus, and a third plurality of input/output terminals, the multiplexer for coupling either the first or the second plurality of input/output terminals to the third plurality of input/output terminals, for allowing output terminals of the data processing system to be shared.

4. The data processing system of claim 1, further comprising:

a bus interface unit coupled between the plurality of front-end channels and the back-end processor, and for coupling the input/output coprocessor to the peripheral bus, for allowing the central processing unit access to the plurality of front-end channels.

5. The data processing system claim 1, further comprising:

a second storage unit coupled to the peripheral bus, the second storage unit for storing instructions and/or data.

6. The data processing system of claim 5, wherein:

the input/output coprocessor further comprises a bus interface unit, coupled between the input/output signal coprocessor and the peripheral bus, wherein the bus interface unit is for allowing the input/output coprocessor access to the peripheral bus for accessing the second storage unit.

7. The data processing system of claim 1, wherein the storage unit is coupled to the back-end processor via a dedicated instruction bus.

8. The data processing system of claim 1, further comprising:

an interrupt processing circuit to indicate whether an interrupt is to be directed to one or both of the back-end processor and the central processing unit.

9. A data processing system, comprising:

a central processing unit for executing first instructions;

a peripheral bus, coupled to the central processing unit; and

an input/output signal coprocessor, coupled to the peripheral bus, the input/output signal coprocessor, comprising

a plurality of front-end channels having a plurality of input/output terminals, the plurality of front-end channels for receiving a time-base value, and in response, for providing a time-base reference for input signals and for generating output signals using the time-base reference, wherein the time-base value is used by the plurality of front-end channels to implement a timer function;

a back-end processor for controlling operation of the plurality of front-end channels in response to executing second instructions, wherein the second instructions are different than the first instructions;

a bus interface unit, coupled to the plurality of front-end channels, to the back-end processor, and to the peripheral bus, for allowing bidirectional communications between the plurality of front-end channels, the back-end processor, and to the peripheral bus;

a visibility bus, coupled to the back-end processor, for providing visibility of internal registers of the back-end processor for program development of the second instructions, wherein the visibility is provided independent of the central processing unit; and

a storage unit, coupled to the back-end processor, for storing the second instructions.

10. The data processing system of claim 9, further comprising a second input/output signal coprocessor, coupled to the peripheral bus and to the visibility bus.

11. The data processing system of claim 9, further comprising:

a multiplexer having a first plurality of input/output terminals coupled to the plurality of input/output terminals of the plurality of front-end channels, a second plurality of input/output terminals coupled to the visibility bus, and a third plurality of input/output terminals, the multiplexer for coupling either the first or the second plurality of input/output terminals to the third plurality of input/output terminals, for allowing output terminals of the data processing to be shared.

12. The data processing system of claim 9, further comprising an interrupt processing circuit for allowing the central processing unit to generate interrupts to the back-end processor.

13. The data processing system claim 9, further comprising:

a second storage unit coupled to the peripheral bus, the second storage unit for storing instructions and/or data.

14. The data processing system of claim 9, wherein the storage unit is coupled to the back-end processor via a dedicated instruction bus.

15. The data processing system of claim 9, further comprising:

an interrupt processing circuit to indicate whether an interrupt is to be directed to one or both of the back-end processor and the central processing unit.

16. The data processing system of claim 15, wherein the interrupt processing circuit is for allowing the central processing unit to generate interrupts to the back-end processor.

17. A data processing system having a central processing unit, an input/output coprocessor, and a peripheral bus for coupling the input/output coprocessor to the central processing unit, the input/output coprocessor comprising:

a plurality of front-end timer channels having a plurality of input/output terminals, each of the plurality of front-end timer channels for receiving a time-base value, and in response, providing a timer function;

a back-end processor for controlling operation of the plurality of front-end timer channels in response to executing instructions, wherein instructions executed by the back-end processor are different than instructions executed by the central processing unit;

a bus interface unit, coupled to the plurality of front-end timer channels, to the back-end processor, and to the peripheral bus, for allowing bidirectional communications between the plurality of front-end timer channels, the back-end processor, and to the peripheral bus;

a visibility bus, coupled to the back-end processor, for providing visibility of internal registers of the back-end processor for instruction programming development, wherein the visibility is provided independent of the central processing unit; and

a storage unit, coupled to the back-end processor via a dedicated bus, the storage unit for storing the instructions.

18. The data processing system of claim 17, wherein each of the plurality of front-end timer channels comprises a plurality of inputs and a plurality of outputs, wherein the plurality of inputs and outputs of each of the plurality of front-end timer channels are serially interconnected to allow the plurality of front-end timer channels to share data and control information and to operate in concert for processing high frequency signals.

19. The data processing system of claim 17, further comprising:

an interrupt processing circuit to indicate whether an interrupt is to be directed to one or both of the back-end processor and the central processing unit.

20. The data processing system of claim 19, wherein the interrupt processing circuit allows the central processing unit to generate interrupts to the back-end processor.

21. The data processing system of claim 19, wherein the interrupt processing is characterized as being a software program mask.