System and method for equalizing data buffer storage and fetch rates of peripheral devices

• US 5,918,073 A
• Filed: 06/27/1997
• Issued: 06/29/1999
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hewitt, Larry D.
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): Mai, Rijue
• Application Number:
  US08/884,432
• Time in Patent Office: 732 Days
• Field of Search: 395/558, 395/872, 395/880, 395/882, 395/308, 395/360, 395/556, 395/325, 395/375, 395/425, 395/750.04, 377/47
• US Class Current: 710/52
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0674 Disk device
• CPC Class Codes: G06F 3/16 Sound input; Sound output speech processing G10L
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence

Abstract

A system and method are presented for equalizing data buffer storage and fetch rates of peripheral devices. A computer system of the present invention includes a central processing unit (CPU), first and second peripheral devices, and a data buffer. The first peripheral device stores data within the data buffer, and the second peripheral device fetches data from the data buffer. A fraction of the data buffer contains unread data (i.e. data stored within the data buffer by the first peripheral device and not yet fetched by the second peripheral device). The first peripheral device includes a reload register, the contents of which determines the rate at which the first peripheral device stores data within the data buffer. The CPU produces a reload value, which is stored within the reload register, such that the rate at which the first peripheral device stores the data within the data buffer is made substantially equal to the rate at which the second peripheral device fetches the data from the data buffer. The data buffer is preferably operated a first-in-first-out manner, and includes a write pointer and a read pointer. The CPU preferably produces the reload value such that approximately half the memory locations within the data buffer contain unread data at any given time.

Claims

1. A computer system, comprising:

a data buffer configured to store data, wherein a fraction of the data buffer contains unread data;

a central processing unit (CPU) operably coupled to the data buffer and configured to determine the fraction of the data buffer containing unread data and to produce a reload value in response to the fraction;

a first peripheral device operably coupled to the data buffer and to the CPU, wherein the first peripheral device is configured to produce a plurality of data prior to storing the plurality of data within the data buffer, and wherein the first peripheral device comprises a reload register, and wherein the rate at which the first peripheral device stores the data within the data buffer is dependent upon the contents of the reload register, and wherein the first peripheral device is configured to receive the reload value and to store the reload value within the reload register;

a second peripheral device operably coupled to the data buffer, wherein the second peripheral device is configured to fetch the data from the data buffer;

wherein the data buffer includes a read and write pointers, and wherein the write pointer is the address of the next available memory location within the data buffer for storing data, and wherein the read pointer is the address of the next memory location containing unread data within the data buffer; and

wherein the CPU modifies the write pointer to account for a portion of the plurality of data produced by the first peripheral device and not yet stored within the data buffer, thereby producing an adjusted write pointer.

2. The computer system as recited in claim 1, wherein the CPU produces the reload value such that the rate at which the first peripheral device stores the data within the data buffer is substantially equal to the rate at which the second peripheral device fetches the data from the data buffer.

3. The computer system as recited in claim 1, wherein the fraction of the data buffer containing unread data is the number of memory locations between the adjusted write pointer and the read pointer.

4. The computer system as recited in claim 1, wherein the data buffer comprises a portion of a system memory operably coupled to the CPU.

5. The computer system as recited in claim 1, wherein the first peripheral device is an audio signal processor, and wherein the second peripheral device is an audio device configured to drive a speaker.

6. A computer system, comprising:

a system memory configured to store data and comprising a data buffer, wherein a fraction of the data buffer contains unread data;

an expansion bus adapted for coupling to one or more peripheral devices;

a bus bridge coupled between the system memory and the expansion bus;

a central processing unit (CPU) coupled to the bus bridge and configured to determine the fraction of the data buffer containing unread data and to produce a reload value in response to the fraction;

a first peripheral device coupled to the expansion bus, wherein the first peripheral device is configured to produce a plurality of data prior to storing the plurality of data within the data buffer, and wherein the first peripheral device comprises a reload register, and wherein the rate at which the first peripheral device stores the data within the data buffer is dependent upon the contents of the reload register, and wherein the first peripheral device is configured to receive the reload value and to store the reload value within the reload register;

a second peripheral device coupled to the bus bridge, wherein the second peripheral device is configured to fetch the data from the data buffer;

wherein the data buffer includes a read and write pointers, and wherein the write pointer is the address of the next available memory location within the data buffer for storing data, and wherein the read pointer is the address of the next memory location containing unread data within the data buffer; and

wherein the CPU modifies the write pointer to account for a portion of the plurality of data produced by the first peripheral device and not yet stored within the data buffer, thereby producing an adjusted write pointer.

7. The computer system as recited in claim 6, wherein the CPU produces the reload value such that the rate at which the first peripheral device stores the data within the data buffer is substantially equal to the rate at which the second peripheral device fetches the data from the data buffer.

8. The computer system as recited in claim 6, wherein the fraction of the data buffer containing unread data is the number of memory locations between the adjusted write pointer and the read pointer.

9. The computer system as recited in claim 6, wherein the data comprises audio data, and wherein the first peripheral device comprises:

a divider circuit comprising the reload register, wherein the divider circuit is configured to produce a frame batch clock signal having a period dependent upon the contents of the reload register; and

a signal processor coupled to receive the frame batch clock signal and configured to produce the audio data, wherein the signal processor initiates processing of a predetermined number of audio signal samples in response to the frame batch clock signal.

10. The computer system as recited in claim 6, wherein the first peripheral device is an audio signal processor, and wherein the second peripheral device is an audio device configured to drive a speaker.

11. A computer system, comprising:

a system memory configured to store data and comprising a data buffer, wherein a fraction of the data buffer contains unread data;

an expansion bus adapted for coupling to one or more peripheral devices;

a bus bridge coupled between the system memory and the expansion bus;

a central processing unit (CPU) coupled to the bus bridge and configured to determine the fraction of the data buffer containing unread data and to produce a reload value in response to the fraction;

a first peripheral device coupled to the expansion bus, wherein the first peripheral device is configured to produce a plurality of audio data prior to storing the plurality of audio data within the data buffer, and wherein the first peripheral device comprises;

a divider circuit comprising;

a reload register; and

a counter coupled to the reload register and coupled to receive a master clock signal having a predetermined period, wherein the divider circuit is configured to produce a frame batch clock signal in response to the master clock signal and having a period dependent upon the contents of the reload register; and

a signal processor coupled to receive the frame batch clock signal and configured to produce the plurality of audio data, wherein the signal processor initiates processing of a predetermined number of audio signal samples in response to the frame batch clock signal;

a second peripheral device coupled to the bus bridge, wherein the second peripheral device is configured to fetch the data from the data buffer;

wherein the data buffer includes a read and write pointers, and wherein the write pointer is the address of the next available memory location within the data buffer for storing data, and wherein the read pointer is the address of the next memory location containing unread data within the data buffer; and

wherein the CPU modifies the write pointer to account for a portion of the plurality of data produced by the first peripheral device and not yet stored within the data buffer, thereby producing an adjusted write pointer.

12. The computer system as recited in claim 11, wherein the first peripheral device is configured to receive the reload value and to store the reload value within the reload register.

13. The computer system as recited in claim 11, wherein the counter produces a plurality of binary output signals representing a binary value, and wherein the binary value is decremented during each cycle of the master clock signal, and wherein when the binary values of all counter output signals are 0, the counter outputs are set to the corresponding values stored within the reload register.

14. The computer system as recited in claim 13, wherein the frame batch clock signal is the value of the most significant binary output signal produced by the counter.

15. The computer system as recited in claim 11, wherein the fraction of the data buffer containing unread data is the number of memory locations between the adjusted write pointer and the read pointer.

16. A method for equalizing the rate at which a first peripheral device stores data within a data buffer and the rate at which a second peripheral device fetches the data from the data buffer, wherein the first peripheral device produces a plurality of data prior to storing the plurality of data within the data buffer, and wherein the data buffer comprises read and write pointers, the method comprising:

obtaining the values of the read and write pointers;

computing an adjusted write pointer, wherein the adjusted write pointer value accounts for a portion of the plurality of data produced by the first peripheral device and not yet stored within the data buffer;

determining the number of memory locations between the adjusted write pointer and the read pointer;

using the number of memory locations between the adjusted write pointer and the read pointer to compute a reload value delta;

adding the reload value delta to a current reload value to compute a new reload value; and

storing the new reload value within a reload register of the first peripheral device.

17. The method as recited in claim 16, wherein the write pointer is the address of the next available memory location within the data buffer for storing data, and wherein the read pointer is the address of the next memory location containing unread data within the data buffer.

18. The method as recited in claim 16, wherein the rate at which the first peripheral device stores the data within the data buffer is dependent upon the contents of the reload register.

19. The method as recited in claim 16, wherein the reload value delta is 0 when the number of memory locations between the adjusted write pointer and the read pointer is approximately equal to half of the total number of memory locations within the data buffer.

20. The method as recited in claim 16, wherein the reload value delta is positive when the number of memory locations between the adjusted write pointer and the read pointer is substantially greater than half of the total number of memory locations within the data buffer.

21. The method as recited in claim 16, wherein the reload value delta is negative when the number of memory locations between the adjusted write pointer and the read pointer is substantially less than half of the total number of memory locations within the data buffer.