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System architecture for and method of dual path data processing and management of packets and/or cells and the like

  • US 5,918,074 A
  • Filed: 07/25/1997
  • Issued: 06/29/1999
  • Est. Priority Date: 07/25/1997
  • Status: Expired due to Term
First Claim
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1. In a CPU or similar data controller system wherein data is interfaced along a common bus connected with common memory and with a plurality of I/O modules receiving and writing into the memory and removing therefrom packets/cells of data, a method of reducing memory and bus access contention and resulting system latency, that comprises, providing each I/O module with a corresponding forwarding engine and transmit queue facility and a separate path for extracting control information from the packet/cell received by that I/O module and providing that control information to the forwarding engine;

  • processing the extracted packet/cell control information in the forwarding engine for making switching, routing and/or filtering decisions while the data thereof is being written into the memory;

    passing the results of the forwarding engine processing to a queue manager for enqueuing and dequeuing receive and transmit queues of each packet/cell, and controlling, through the corresponding I/O module transmit queue facility, the interfacing with the appropriate egress I/O module to which to transmit the packet/cell data, all without contention with and independent of the transfer of packet/cell data into and from the memory.

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