Method of forming vertical trench-gate semiconductor devices having self-aligned source and body regions

• US 5,918,114 A
• Filed: 05/13/1997
• Issued: 06/29/1999
• Est. Priority Date: 05/22/1996
• Status: Expired due to Term

• Current Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Yong-Cheol, Jeon, Chang-Ki
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/855,459
• Time in Patent Office: 777 Days
• Field of Search: 438/134, 438/270, 438/274, 438/301, 438/305, 438/598
• US Class Current: 438/134
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Methods of forming vertical trench-gate semiconductor devices include the steps of patterning an oxidation resistant layer having an opening therein, on a face of a semiconductor substrate, and then forming a trench in the semiconductor substrate, opposite the opening in the oxidation resistant layer. An insulated gate electrode is then formed in the trench. The face of the semiconductor substrate is then oxidized to define self-aligned electrically insulating regions in the opening and at a periphery of the patterned oxidation resistant layer. Here, the patterned oxidation resistant layer is used as an oxidation mask so that portions of the substrate underlying the oxidation resistant layer are not substantially oxidized. Source and body region dopants of first and second conductivity type, respectively, are then implanted into the substrate to define preliminary source and body regions which extend adjacent a sidewall of the trench. During the implanting step, the electrically insulating regions are used as a self-aligned implant mask. The implanted dopants are then diffused into the substrate to define source and body regions adjacent upper and intermediate portions of the sidewall of the trench, respectively.

Claims

1. A method of forming a semiconductor switching device, comprising the steps of:

patterning an oxidation resistant layer to define an opening therein, on a face of a semiconductor substrate;

forming a trench in the semiconductor substrate, opposite the opening in the oxidation resistant layer;

forming an electrode in the trench;

oxidizing the semiconductor substrate to form electrically insulating regions at a periphery of the patterned oxidation resistant layer, using the patterned oxidation resistant layer as an oxidation mask; and

implanting dopants of first and second conductivity type into the semiconductor substrate to define preliminary source and body regions therein extending adjacent a sidewall of the trench, using the electrically insulating regions as an implant mask.

2. The method of claim 1, wherein said oxidizing step comprises oxidizing the electrode and the face of the semiconductor substrate to form electrically insulating regions at the opening and at the periphery of the patterned oxidation resistant layer.

3. The method of claim 2, wherein said step of implanting dopants of first and second conductivity type is followed by the step of diffusing the implanted dopants of first and second conductivity type to define a source region of first conductivity type extending adjacent the face of the semiconductor substrate and a body region of second conductivity type extending between the source region and a bottom of the trench.

4. The method of claim 2, wherein said step of patterning an oxidation resistant layer comprises the steps of:

forming a first oxide layer on the face;

forming a first nitride layer on the first oxide layer, opposite the face; and

etching the first nitride layer to expose the first oxide layer at a periphery thereof.

5. The method of claim 4, wherein said step of etching the first nitride layer is followed by the step of implanting dopants of second conductivity type into the semiconductor substrate to define a preliminary contact region of second conductivity type therein, using the first nitride layer as an implant mask.

6. The method of claim 5, wherein said step of patterning an oxidation resistant layer further comprises etching the first nitride layer to define the opening, after said step of implanting dopants of second conductivity type into the face;

and wherein said trench forming step comprises etching the semiconductor substrate at a location extending opposite the opening in the first nitride layer.

7. The method of claim 6, wherein said electrode forming step comprises oxidizing a sidewall of the trench and then forming a polysilicon gate electrode of first conductivity type in the trench.

8. The method of claim 7, wherein said oxidizing step comprises oxidizing the face of the semiconductor substrate and the polysilicon gate electrode to form electrically insulating regions at the opening and at the periphery of the first nitride layer.

9. The method of claim 5, wherein said step of implanting dopants of second conductivity type into the semiconductor substrate is followed by the step of forming a second oxide layer on the first nitride layer and on a portion of the first oxide layer extending opposite the preliminary contact region;

and wherein said step of patterning an oxidation resistant layer further comprises etching the second oxide layer, the first nitride layer and the first oxide layer, in sequence, to define the opening and expose the face of the semiconductor substrate.

10. The method of claim 9, wherein said electrode forming step comprises oxidizing a sidewall of the trench and then forming a polysilicon gate electrode in the trench.

11. The method of claim 10, wherein said oxidizing step comprises oxidizing the polysilicon gate electrode and oxidizing the preliminary contact region at the face of the semiconductor substrate, to form electrically insulating regions at the opening and at the periphery of the first nitride layer.

12. The method of claim 11, wherein said step of implanting dopants of first and second conductivity type is followed by the step of diffusing the dopants in the preliminary source, body and contact regions into the semiconductor substrate to define a source region of first conductivity type extending adjacent the face of the semiconductor substrate, a body region of second conductivity type extending between the source region and a bottom of the trench and a contact region of second conductivity type forming rectifying and non-rectifying junctions with the source and body regions, respectively.

13. A method of forming a semiconductor switching device, comprising the steps of:

forming a first oxide layer on a face of a semiconductor substrate containing a drift region of first conductivity type therein extending to the face;

forming a first nitride layer on the first oxide layer, opposite the face;

etching the first nitride layer to expose the first oxide layer at a periphery thereof;

then

implanting dopants of second conductivity type into the drift region to define a preliminary contact region therein, using the first nitride layer as an implant mask;

then

etching the first nitride layer and first oxide layer to define an opening therein exposing the face of the semiconductor substrate;

etching the semiconductor substrate at the opening to define a trench therein;

forming an insulated gate electrode in the trench;

oxidizing the insulated gate electrode and the preliminary contact region to form self-aligned electrically insulating regions therein, using the first nitride layer as an oxidation mask;

implanting dopants of first and second conductivity type into the drift region at respective first and second energies to define preliminary source and body regions therein, using the electrically insulating regions as an implant mask; and

diffusing the dopants in the preliminary source, body and contact regions into the drift region to define a source region extending adjacent an upper portion of a sidewall of the trench, a body region extending adjacent an intermediate portion of the sidewall of the trench and a contact region forming a non-rectifying junction with the body region at a location spaced from the sidewall of the trench.

14. The method of claim 13, wherein said step of implanting dopants of first and second conductivity type into the drift region is preceded by the step of removing the first nitride layer.

15. The method of claim 14, wherein said step of implanting dopants of first and second conductivity type into the drift region comprises implanting dopants through the first oxide layer and into the face of the semiconductor substrate.

16. The method of claim 14, wherein said step of forming an insulated gate electrode in the trench comprises thermally oxidizing the sidewall of the trench to form a gate insulating layer and then depositing polycrystalline silicon into the trench and then planarizing the polycrystalline silicon using the first nitride layer as an planarization stop.

17. The method of claim 16, wherein said step of depositing polycrystalline silicon into the trench comprises in-situ doping the polycrystalline silicon by exposing the polycrystalline silicon to a POCI₃ atmosphere.

18. The method of claim 14, wherein said step of etching the first nitride layer and first oxide layer to define an opening therein is preceded by the step of depositing a second oxide layer on the first nitride layer and on the preliminary contact region.

19. The method of claim 18, wherein said step of forming an insulated gate electrode in the trench comprises thermally oxidizing the sidewall of the trench to form a gate insulating layer and then depositing polycrystalline silicon into the trench and then planarizing the polycrystalline silicon using the first nitride layer as an planarization stop.

20. The method of claim 19, wherein said step of depositing polycrystalline silicon into the trench comprises in-situ doping the polycrystalline silicon by exposing the polycrystalline silicon to a POCI₃ atmosphere.