Process for forming gate oxides possessing different thicknesses on a semiconductor substrate

• US 5,918,116 A
• Filed: 05/09/1997
• Issued: 06/29/1999
• Est. Priority Date: 11/30/1994
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Chittipeddi, Sailesh
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): SULSKY, MARTIN S
• Application Number:
  US08/853,210
• Time in Patent Office: 781 Days
• Field of Search: 438/199, 438/197, 438/142, 438/981
• US Class Current: 438/199
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

Gate oxides having different thicknesses are grown on a semiconductor layer by the process which comprises forming a semiconductor layer on a substrate, growing an oxide layer on the semiconductor layer, exposing a selected area of the oxide layer, amorphizing the semiconductor layer underlying the exposed oxide layer, removing the oxide layer to expose the semiconductor layer having both amorphized and non-amorphized regions and growing gate oxide on the amorphized and non-amorphized regions of the semiconductor layer. Gate oxide grown on the amorphized regions will be thicker than gate oxide grown on the non-amorphized regions.

The process of the invention obviates the need for special integrated circuit manufacturing design modifications and can be utilized to fabricate a wide variety of devices, in particular, MOS-type devices.

Claims

1. A process for fabricating an integrated circuit comprising the steps of:

(a) growing a semiconductor layer on a substrate;

(b) forming an oxide layer upon the semiconductor layer;

(c) amorphizing a selected area of the semiconductor layer to form an amorphized underlayer;

(d) removing the oxide layer to expose the semiconductor layer having both amorphized and non-amorphized regions;

(e) simultaneously growing gate oxide on the amorphized and non-amorphized regions of the semiconductor layer, including growing gate oxide on the amorphized underlayer, wherein the amorphized underlayer causes a differential in thickness in the gate oxide for forming the gate oxide of a first thickness on the non-amorphized region and of a second thickness greater than the first thickness on the amorphized region of the semiconductor layer to provide regions of the semiconductor layer adapted for different operating voltages.

2. The process of claim 1 wherein the substrate is a silicon wafer.

3. The process of claim 1 wherein the semiconductor layer is epitaxial silicon, polycrystalline silicon or silicon-germanium.

4. The process of claim 1 further comprising, prior to forming the oxide layer, the steps of growing and removing a sacrificial thermal oxide on the semiconductor layer to remove defects from the surface of the semiconductor layer.

5. The process of claim 1 wherein the semiconductor layer is provided with a plurality of device tubs prior to growing the oxide layer.

6. The process of claim 1 wherein the oxide layer is formed on the substrate by heating the substrate to a temperature ranging from about 600°

C. to about 1200°

C. and oxidizing the substrate.

7. The process of claim 1 wherein the oxide layer possesses a thickness which ranges from about 60 to about 500 Å

.

8. The process of claim 1 wherein the oxide layer possesses a thickness which ranges from about 80 to about 200 Å

.

9. The process of claim 1 wherein the step of amorphizing the selected area of the semiconductor layer is carried out by depositing a masking layer on the oxide layer and patterning the masking layer to provide a window which exposes the selected area of the oxide layer and thereafter implanting ions in the semiconductor layer underlying the exposed oxide layer.

10. The process of claim 9 wherein the ions are selected from the group consisting of silicon, fluorine, arsenic and mixtures thereof.

11. The process of claim 9 wherein the ions are implanted via ion mixing implantation.

12. The process of claim 9 wherein the ions are implanted at a dose ranging from about 1×

10¹² to about 5×

10¹⁶ ions per cm².

13. The process of claim 9 wherein the ions are implanted at a dose ranging from about 1×

10¹⁵ to about 5×

10¹⁵ ions per cm².

14. The process of claim 9 wherein the ions are implanted at an energy ranging from about 5 to about 500 keV.

15. The process of claim 9 wherein the ions are implanted at an energy ranging from about 20 to about 50 keV.

16. The process of claim 1 wherein the oxide layer is annealed prior to being removed.

17. The process of claim 1 wherein the gate oxide is grown on the amorphized and non-amorphized regions of the semiconductor layer by heating the substrate to a temperature ranging from about 600°

C. to about 1200°

C. and oxidizing the substrate.

18. The process of claim 1 wherein the gate oxide grown on the amorphized regions of the semiconductor layer possesses a thickness which ranges from about 40 to about 500 Å

.

19. The process of claim 1 wherein the gate oxide grown on the amorphized regions of the semiconductor layer possesses a thickness which ranges from about 100 to about 160 Å

.

20. The process of claim 1 wherein the gate oxide grown on the non-amorphized regions of the semiconductor layer possesses a thickness which ranges from about 20 to about 400 Å

.

21. The process of claim 1 wherein the gate oxide grown on the non-amorphized regions of the semiconductor layer possesses a thickness which ranges from about 80 to about 130 Å

.

22. The process of claim 1 further comprising the step of:

(f) fabricating devices on the gate oxides of different thicknesses for operation with a plurality of different operating voltages.

23. The process of claim 22 wherein the devices are selected from the group consisting of dual voltage, mixed signal, pure analog and digital devices.

24. The process of claim 22 wherein the devices are MOS devices.

25. The process of claim 22 wherein at least one device operates at a voltage which ranges from about 1.8 to about 3.3 V and at least one device operates at a voltage of about 5 V.