MOS transistor with shield coplanar with gate electrode

• US 5,918,137 A
• Filed: 04/27/1998
• Issued: 06/29/1999
• Est. Priority Date: 04/27/1998
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Spectrian Corp. (REMEC, Inc.)
• Inventors: Hebert, Francois, Ng, Sze Him
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Blum, David S.
• Application Number:
  US09/067,656
• Time in Patent Office: 428 Days
• Field of Search: 438/454, 438/159, 438/183, 438/267, 257/294, 257/340
• US Class Current: 438/454
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A MOS transistor including a gate electrode on a gate oxide over a channel region between a source region and a drain region also includes a shield electrode at least partially on the gate oxide adjacent to, self-aligned with, and at least partially coplanar with the gate electrode and between the gate electrode and drain region. Placing the shield electrode on the gate oxide improves the gate-drain shielding, reduces the gate-drain capacitance, Cgd, and reduces hot electron related reliability hazard.

Claims

1. A method of fabricating a MOS transistor with a self-aligned gate-drain electrode adjacent to a gate electrode and at least partially formed on a gate oxide, the method comprising the steps of:

a) providing a silicon substrate of one conductivity type with a surface well region of a second conductivity type,

b) forming source and channel regions in said well region,

c) forming a gate oxide layer on a surface of the well region,

d) forming a gate electrode on the gate oxide layer over the channel region, and

e) forming a gate-drain shield electrode on the oxide layer adjacent to and spaced from the gate electrode at least partially coplanar with the gate electrode and overlying a drain region comprising a portion of the surface well region.

2. A method of fabricating a MOS transistor with a self-aligned shield electrode adjacent to a gate electrode and at least partially formed on a gate oxide, the method comprising the steps of:

a) providing a silicon substrate of one conductivity type with a surface well region of a second conductivity type,

b) forming source and channel regions in said well region,

c) forming a gate oxide layer on a surface of the well region,

d) forming a gate electrode on the gate oxide layer over the channel region, and

e) forming a shield electrode on the gate oxide layer adjacent to and spaced from the gate electrode and at least partially coplanar with the gate electrode, including depositing a conductive layer on the gate oxide and then etching the conductive layer to form both the gate electrode and the shield electrode on the same step.

3. The method as defined by claim 2 wherein step e) includes depositing a polysilicon layer on the gate oxide and depositing a metal silicide on the polysilicon layer.

4. The method as defined by claim 2 and further including the step of growing an oxide in the gate oxide which is thicker than the gate oxide, the shield electrode overlapping the thicker oxide away from the gate electrode and overlapping the gate oxide near the gate electrode.

5. The method as defined by claim 4 wherein the thicker oxide is grown after step e).

6. The method as defined by claim 4 wherein the thicker oxide is grown before step e).

7. The method as defined by claim 6 wherein the thicker oxide is grown by a LOCOS process.

8. The method as defined by claim 6 wherein the thicker oxide is formed on the gate oxide and then selectively etched to form a thicker bump on the gate oxide.

9. The method as defined by claim 2 and further including the step of forming a drain region in said well region.

10. The method as defined by claim 9 wherein said silicon substrate includes an epitaxial layer of the one conductivity type.

11. The method as defined by claim 10 wherein the one conductivity type is P type and the second conductivity type is N type.

12. The method as defined by claim 10 and further including the step of forming a plug of the one conductivity type extending through the epitaxial layer to the substrate, a channel region being formed in the well region by annealing the plug and driving dopants of the one conductivity type into the well region.

13. The method as defined by claim 12 and further including the steps of forming metal contacts to the source region and to the drain region.

14. The method as defined by claim 13 and further including the step of forming a dielectric passivation layer over the surface of the MOS transistor.