Promoting local memory accessing and data migration in non-uniform memory access system architectures

• US 5,918,249 A
• Filed: 12/19/1996
• Issued: 06/29/1999
• Est. Priority Date: 12/19/1996
• Status: Expired due to Term

• Current Assignee: Transpacific Digital Systems LLC (Intellectual Ventures LLC)
• Original Assignee: NCR Corporation
• Inventors: Cox, John S., Waters, John H.
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): GOODARZI, NASSER MOAZZAMI
• Application Number:
  US08/772,039
• Time in Patent Office: 922 Days
• Field of Search: 711/203, 711/170, 711/3
• US Class Current: 711/203
• CPC Class Codes: G06F 12/1072 Decentralised address translation, e.g. in distributed shared memory systems
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture

Abstract

A non-uniform memory accessing (NUMA) based multiprocessor system that promotes local memory accessing and data migration to local processor nodes. The system includes mechanisms to re-map virtual and physical addresses to promote local memory accessing and implements a least recently used memory allocation mechanism to age non-local memory accesses out of memory to be re-read into local memory, which promotes data migration to local memory on processor nodes.

Claims

1. A method for managing memory accesses in a NUMA based multiprocessor system including a plurality of processor nodes each having at least one processor and memory associated with the at least one processor, and a data storage subsystem, that promotes local memory accessing and migration of data to be retrieved by a process to a processor node running the process, the method comprising:

running a process on a processor node in the system;

determining if physical memory addresses for data to be retrieved by the running process is in the memory associated with the processor node; and

re-assigning physical memory addresses corresponding to the memory of the processor node running the process for the data to be retrieved by the process running on the processor node to the virtual addresses of the data, if the physical memory addresses do not correspond to the memory associated with the processor node running the process.

2. The method according to claim 1, wherein an operating system of the system re-assigns the physical memory addresses.

3. The method according to claim 1 further comprising:

determining if the re-assigned physical memory has available space to store the data; and

purging data from re-assigned physical memory associated with the re-assigned physical memory addresses if space to store the data is unavailable.

4. The method according to claim 3, wherein the data is purged from the re-assigned physical memory using an LRU method.

5. The method according to claim 4, wherein data stored in the re-assigned memory is time stamped and the LRU method purges data having the oldest time stamp.

6. A non-uniform memory accessing (NUMA) based multiprocessor system that promotes local memory accessing and data migration of data used by a process to a processor node running the process, comprising:

a plurality of processor nodes interconnected through a common bus, each processor node having at least one processor and memory associated with the at least one processor; and

a memory management mechanism to re-map virtual and physical memory addresses such that memory accessing by a process running on one of the plurality of processor nodes is to the memory associated with the processor node running the process, and to implement a least recently used memory allocation mechanism to remove aged data in the memory space associated with the re-mapped physical memory addresses if the space is unavailable.

7. A non-uniform memory accessing (NUMA) based multiprocessor system that promotes local memory accessing and data migration of data used by a process to a processor node running the process, comprising:

a plurality of processor nodes interconnected through a common bus, each processor node having at least one processor and memory associated with the at least one processor; and

a memory management means for re-mapping virtual and physical memory addresses such that memory accesses by a process running on one of the plurality of processor nodes is to the memory associated with the processor node running the process, and for removing aged data in the memory associated with the processor node running the process if memory space associated with the re-mapped physical memory addresses is unavailable.

8. The system according to claim 7, wherein said memory management means uses least recently used memory allocation means for removing the aged data in the memory associated with the processor node running the process if the memory space associated with the re-mapped physical memory addresses is unavailable.