Method and apparatus for preloading different default address translation attributes

• US 5,918,251 A
• Filed: 12/23/1996
• Issued: 06/29/1999
• Est. Priority Date: 12/23/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Yamada, Koichi, Hammond, Gary N.
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): GOODARZI, NASSER MOAZZAMI
• Application Number:
  US08/771,845
• Time in Patent Office: 918 Days
• Field of Search: 711/207, 711/3, 711/205, 395/500, 395/833
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 2212/654 Look-ahead translation

Abstract

A method and apparatus for streamlining the installation of virtual to physical address translations into a translation unit. According to one aspect of the invention, an apparatus for use in a computer system is provided that generally includes a translation unit, a default attribute storage area, and a preload unit. The translation unit stores translations for translating virtual addresses into physical addresses, and each of these translations includes an attribute field. The default translation attribute storage area stores a number of default translation attributes. The preload unit is coupled to the default translation unit and the translation unit. In response to receiving a signal from the translation unit indicating a translation for a virtual address is not stored in the translation unit, the preload unit transmits the appropriate default translation attribute to the translation unit.

Claims

1. An apparatus for use in a computer system, said apparatus comprising:

an address translation unit configured to store a plurality of translations for translating virtual addresses into physical addresses, each of said translations including an attribute field to define an attribute for its translation;

a default translation attribute storage unit configured to store a plurality of default translation attributes, each of the default translation attributes being associated with a selected set of virtual addresses and utilized when a translation for a particular virtual address is not present in said address translation unit; and

a preload unit coupled to said default translation attribute storage unit and said address translation unit for preloading a corresponding default translation attribute for use by said address translation unit, but having the default translation attribute replaced if not correct for the translation of the particular virtual address.

2. The apparatus of claim 1, wherein each default translation attribute identifies at least one of a page size, a caching protocol, and a protection key.

3. The apparatus of claim 1 further comprising:

a page miss handler coupled to said address translation unit for generation of a physical page number field for the translation when a page miss occurs in said address translation unit.

4. The apparatus of claim 1, wherein said default translation attribute storage area is comprised of a set of registers.

5. A processor comprising:

a translation look-aside buffer for translating a virtual address into a physical address;

a translation look-aside buffer installation storage unit coupled to said translation look-aside buffer and including a translation attribute field to define an attribute when translating the virtual address to the physical address;

a set of registers, each including a default translation attribute field; and

a preload unit coupled to said set of registers and said translation look-aside buffer installation storage unit for preloading a corresponding default translation attribute field for use by said translation look-aside buffer installation storage unit for installation into said translation look-aside buffer, but having the default translation attribute field replaced if not correct for the translation of the virtual address.

6. The processor of claim 5, wherein N bits of said virtual address are used to identify a corresponding register in said set of registers having the corresponding default translation attribute field.

7. The processor of claim 5, wherein data stored in said translation attribute field identifies at least one of a page size, a caching protocol, and a protection key associated with a memory.

8. The processor of claim 5 further comprising a page miss handler coupled to said translation look-aside buffer for generation of a page number for the translation when a page miss occurs in said translation look-aside buffer.

9. The processor of claim 5 further comprising an event handling unit coupled to said translation look-aside buffer for invoking a software page miss handler for generation of a page number for the translation when a page miss occurs in said translation look-aside buffer.

10. A computer system comprising:

a processor including,

a translation look-aside buffer for translating a virtual address into a physical address,

a translation look-aside buffer installation storage unit coupled to said translation look-aside buffer and including a translation attribute field to define an attribute when translating the virtual address to the physical address,

a set of registers, each register including a default translation attribute field, and

a preload unit coupled to said set of registers and said translation look-aside buffer installation storage unit for preloading a corresponding default translation attribute field for use by said translation look-aside buffer installation storage unit for installation into said translation look-aside buffer, but having he default translation attribute field replaced if not correct for the translation of the virtual address; and

a memory coupled to said processor which is accessed by the physical address generated by the processor.

11. The computer system of claim 10, wherein N bits of said virtual address are used to identify a corresponding register in said set of registers having the corresponding default translation attribute field.

12. The computer system of claim 10, wherein data stored in said translation attribute field identifies at least one of a page size, a caching protocol, and a protection key associated with said memory.

13. The computer system of claim 10 further comprising a page miss handler coupled to said translation look-aside buffer for generation of a page number for the translation when a page miss occurs in said translation look-aside buffer.

14. The computer system of claim 10, said memory having resident therein a software page miss handler for execution by said processor to load a correct translation attribute field when the default translation attribute field is not correct.

15. A method for preloading a translation attribute field for use when translating a virtual address to a physical address comprising:

detecting if a translation for the virtual address is presently available;

selecting one of a plurality of stored default translation attributes as a corresponding default translation attribute for the translation attribute field;

preloading the corresponding default translation attribute when the translation of the virtual address is not presently available to generate a new translation;

using the preloaded default translation attribute if correct, but if not, overwriting it with the correct translation attribute.

16. The method of claim 15 further comprising:

storing a virtual page number for the translation of the virtual address.

17. The method of claim 15, wherein said preloading includes preloading the default translation attribute to identify at least one of a page size, a caching protocol, and a protection key.

18. The method of claim 15 wherein said determining includes executing a software page miss handler.