Vital serial link

• US 5,919,237 A
• Filed: 12/03/1996
• Issued: 07/06/1999
• Est. Priority Date: 12/04/1995
• Status: Expired due to Term

• Current Assignee: General Railway Signal Company
• Original Assignee: General Railway Signal Company
• Inventors: Balliet, James B.
• Primary Examiner(s): Cuchlinski, Jr., William A.
• Assistant Examiner(s): ARTHUR JEANGLAUDE, GERTRUDE
• Application Number:
  US08/759,770
• Time in Patent Office: 945 Days
• Field of Search: 701/19, 701/24, 701/33, 701/39, 701/43, 395/200.3, 395/200.62, 364/131, 364/132, 364/133
• US Class Current: 701/19
• CPC Class Codes: B61L 27/70 Details of trackside communication
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A vital serial link for linking a plurality of data processors which act on information communicated in the form of link information signals, into a vital serial communications network, including at least two vital serial controllers, one for each direction of transmission, in the vital serial link, each controller including a means for storing a plurality of link parameters, each of the link parameters including a numerical relationship indicating that a specified first processor originated a signal and that a designated second processor is to receive said signal, a unique numerical relationship being provided for each possible combination of signal originating processor and signal receiving processor; whereby, upon receipt of a signal, the signal receiving processor can discriminate signals sent to the receiving processor, and determine which processor in said network was the signal originating processor. The link further includes communicating means for communicating signals, including the link parameters, between the data processors of the network.

Claims

1. A vital serial link for linking, in a railway signaling system having two opposite directions of transmission, a plurality of data processors which act on information communicated in the form of link information signals, into a vital serial communications network, said vital serial link comprising:

at least two vital serial controllers, connected to respective processors, each controller operating in both directions of transmission, said controllers being connected in back-to-back relationship in the vital serial link, each of said controllers including;

means for storing a plurality of link parameter signals, each of said link parameter signals including a unique numerical relationship indicating that a specified first processor originated a signal and that a designated second processor is to receive said signal, the unique numerical relationship being provided for each possible combination of signal-originating processor and signal-receiving processor;

wherein

upon receipt of a signal, said signal receiving processor can discriminate signals sent to said receiving processor, and determine which processor in said network was the signal originating processor;

said vital serial link further comprising communicating means for communicating signals, including said link parameter signals, between said plurality of data processors in said network.

2. The link of claim 1 wherein said storing means is an EPROM.

3. The link of claim 1 wherein said communications means is a twisted pair.

4. The link of claim 1 wherein said link parameters are in the form of 32 bit codewords.

5. The link of claim 1 wherein said codewords are assigned by a Computer Aided Application software package.

6. The link of claim 1 further comprising means for enabling each of said vital serial controllers to generate check information indicating that a data memory of a processor has been cleared of prior link information, and that system memory and application memory integrity has been maintained, each time a subsequent link information signal is received.

7. The link of claim 6 wherein check information is generated in the form of link keys.

8. The link of claim 7 wherein a first processor generating a signal originates a first check key that is added to said check information, and that each subsequent processor receiving said signal augments said check information with an additional link key.

9. The link of claim 8 wherein a checkword, augmented with a link key by an augmenting processor is assigned as a link key for said augmenting processor.

10. The link of claim 9 wherein any failures indicated in said link messages corrupts said link key at a point of failure and causes all subsequent processors receiving the corrupted link key to assign a link parameter corresponding to a most restrictive state.

11. The link of claim 1 further comprising means to provide a dynamic offset function, said dynamic offset function-producing means including a set of offset parameters embedded within each signal transmitted over said link, an offset parameter in a subsequent signal having a cycle offset by a predetermined amount relative to a previous signal, freshness of any received signal being determined by each controller through formation of a system checkword including both a current and previous offset parameter and determining whether there is offset between the cycles thereof.