Method for assembling an integrated circuit chip package having at least one semiconductor device

• US 5,919,329 A
• Filed: 10/02/1998
• Issued: 07/06/1999
• Est. Priority Date: 10/14/1997
• Status: Expired due to Term

• Current Assignee: W. L. Gore & Associates (W.L. Gore & Associates)
• Original Assignee: Gore Enterprise Holdings Incorporated
• Inventors: Fischer, Paul J., Petefish, William G., Sylvester, Mark F., Banks, Donald R., Pofahl, Ronald G.
• Primary Examiner(s): RAIMUND, CHRISTOPHER W
• Application Number:
  US09/166,056
• Time in Patent Office: 277 Days
• Field of Search: 156/281, 156/327, 156/330, 438/115, 438/118
• US Class Current: 156/281
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/4864 Cleaning, e.g. removing of solder
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/142 Metallic substrates having insulating layers
• CPC Class Codes: H01L 23/3733 having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures H01L23/3732, H01L23/3737 take precedence
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01025 Manganese [Mn]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

The present invention generally relates to the field of integrated circuit chip packaging. More particularly, the present invention relates to methods of manufacturing integrated circuit chip packages, and methods for electrically connecting and bonding or attaching semiconductor devices to an integrated circuit chip.

Claims

1. A method for assembling an integrated circuit chip package having an organic package substrate and an integrated circuit chip, said method comprising the following steps:

providing an organic package substrate having,

A) a metal core having at least one clearance formed therethrough,

B) at least one dielectric layer disposed on each of top and bottom surfaces of said metal core, said at least one dielectric layer being an expanded polytetrafluoroethylene material having a mixture disposed within said material, said mixture containing particulate filler and an adhesive resin,

C) at least one conductive layer disposed on each of said dielectric layers and at least one conductive via electrically connecting said conductive layers, and

D) a plurality of interconnect pads adapted to electrically and mechanically mount an integrated circuit chip;

providing an integrated circuit chip having disposed on a surface thereof a plurality of solder interconnect members;

locating the integrated circuit chip on said organic package substrate in an orientation wherein each of said solder interconnect members of said integrated circuit chip are aligned with an individual interconnect pad of said organic package substrate;

heating the organic package substrate and the integrated circuit chip to a temperature of less than 260°

C. to thereby mechanically and electrically attach the integrated circuit chip to the organic package substrate;

cleaning said integrated circuit chip and said organic package substrate with a solvent liquid;

plasma cleaning said integrated circuit chip and said organic package substrate;

heating said integrated circuit chip and said organic package substrate to a temperature ranging from about 70°

C. to about 90°

C.;

providing an underfill bonding material having an elastic modulus less than about 10 Gpa, a Poisson'"'"'s Ratio less than about 0.29, a coefficient of thermal expansion of less than about 32 ppm/°

C., and a linear cure shrinkage of less than about 0.2%;

disposing said underfill bonding material between said integrated circuit chip and said organic package substrate; and

curing said underfill bonding material.