Semiconductor device and method of making

• US 5,919,713 A
• Filed: 12/14/1994
• Issued: 07/06/1999
• Est. Priority Date: 01/28/1994
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ishii, Masanori, Suzuki, Yoji, Suzuki, Hidetake
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): MULPURI, SAVITRI
• Application Number:
  US08/355,481
• Time in Patent Office: 1,665 Days
• Field of Search: 437/226, 437/227, 437/974, 437/225, 437/228, 148/DIG. 28, 148/DIG. 135, 148/DIG. 12, 257/620, 156/644.1
• US Class Current: 438/464
• CPC Class Codes: B05D 7/146 to metallic pipes or tubes processes for coating the interior of pipes B05D7/222
• CPC Class Codes: C08G 59/50 Amines
• CPC Class Codes: C08G 59/5006 aliphatic
• CPC Class Codes: C08G 59/54 Amino amides>
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/10336 : Aluminium gallium arsenide [AlGaAs]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A method for fabricating a semiconductor device including the steps of forming a plurality of semiconductor chips on a semiconductor substrate, forming a connection part such that the connection part connects the semiconductor chips with each other across a dicing line, bonding the semiconductor substrate upon a support substrate, removing the dicing region while maintaining the semiconductor chips in a state such that the semiconductor chips are bonded upon the support substrate, detaching the plurality of semiconductor chips from the support substrate while maintaining an alignment between the semiconductor chips, and separating the semiconductor chips from each other by eliminating the connection part.

Claims

1. A method for fabricating a semiconductor device, comprising the steps of:

(a) forming a plurality of semiconductor devices on a semiconductor substrate, such that said semiconductor devices are separated from each other by a dicing region;

(b) forming a connection part on said dicing region such that said connection part mechanically connects said semiconductor devices with each other;

(c) separating said plurality of semiconductor devices from each other, except for said connection part, by selectively removing said dicing region; and

(d) separating said plurality of semiconductor devices from each other by breaking a mechanical connection formed by said connection part,

wherein said step (c) comprises a sub-step of bonding said semiconductor substrate upon a support substrate by means of a bonding medium such that each of said semiconductor devices on said semiconductor substrate has a surface thereof engaged upon a surface of said support substrate, wherein said step of removing said dicing region is conducted, in said step (c), in a state that said semiconductor devices are bonded upon said support substrate; and

wherein said step (d) comprises the sub-steps of;

detaching said semiconductor devices from said support substrate by removing said bonding medium while maintaining the state in which said semiconductor devices are connected with each other mechanically by said connection part;

bonding a rear side of said semiconductor devices, after being detached from said support substrate, upon a sticky medium; and

disconnecting said connection part.

2. A method as claimed in claim 1, wherein said step (d) includes a step for deforming said sticky medium to break said connection part.

3. A method for fabricating a semiconductor device, comprising the steps of:

(a) forming a plurality of semiconductor devices on a semiconductor substrate, such that said semiconductor devices are separated from each other by a dicing region;

(b) forming a connection part on said dicing region such that said connection part mechanically connects said semiconductor devices with each other;

(c) separating said plurality of semiconductor devices from each other, except for said connection part, by selectively removing said dicing region; and

(d) separating said plurality of semiconductor devices from each other by breaking a mechanical connection formed by said connection part,

wherein said step (b) comprises the sub-steps of;

depositing a protective layer upon said semiconductor substrate such that said protective layer covers each of said semiconductor devices including said dicing region; and

patterning said protective layer to form the connection part such that said connection part connects said semiconductor devices with each other.

4. A method as claimed in claim 3, wherein said step of patterning said protective layer is conducted to form a device surface region that is a part of said protective layer covering a principal surface of said semiconductor device, such that said connection part is isolated from said device surface region.

5. A method for fabricating a semiconductor device, comprising the steps of:

(a) forming a plurality of semiconductor devices on a semiconductor substrate, such that said semiconductor devices are separated from each other by a dicing region;

(b) forming a connection part on said dicing region such that said connection part mechanically connects said semiconductor devices with each other;

(c) separating said plurality of semiconductor devices from each other, except for said connection part, by selectively removing said dicing region; and

(d) separating said plurality of semiconductor devices from each other by breaking a mechanical connection formed by said connection part,

wherein said step (b) comprises a sub-step of depositing a layer having a composition different from said semiconductor substrate, upon said semiconductor substrate, such that said layer covers continuously those regions of said substrate in which said semiconductor devices are formed and those regions in which said dicing region is formed, and wherein said step (b) includes mounting a support substrate over said layer formed by said sub-step.

7. A method as claimed in claim 5, wherein said step of etching is conducted while using a metal layer covering a rear principal surface of said semiconductor devices as a mask.

6. A method for fabricating a semiconductor device, comprising the steps of:

(a) forming a plurality of semiconductor devices on a semiconductor substrate, such that said semiconductor devices are separated from each other by a dicing region;

(b) forming a connection part on said dicing region such that said connection part mechanically connects said semiconductor devices with each other;

(c) separating said plurality of semiconductor devices from each other, except for said connection part, by selectively removing said dicing region; and

(d) separating said plurality of semiconductor devices from each other by etching away a mechanical connection formed by said connection part.

8. A method for fabricating a semiconductor device, comprising the steps of:

(a) forming a plurality of semiconductor devices on a semiconductor substrate, such that said semiconductor devices are separated from each other by a dicing region;

(b) forming a connection part on said dicing region such that said connection part mechanically connects said semiconductor devices with each other;

(c) separating said plurality of semiconductor devices from each others, except for said connection part, by selectively removing said dicing region; and

(d) separating said plurality of semiconductor devices from each other by breaking a mechanical connection formed by said connection part,

wherein said step (c) comprises a sub-step of bonding said semiconductor substrate upon a support substrate by means of a bonding medium such that each of said semiconductor devices on said semiconductor substrate has a surface thereof engaged upon a surface of said support substrate, wherein said step of removing said dicing region is conducted in said step (c), in a state that said semiconductor devices are bonded upon said support substrate;

wherein said step (d) comprises the sub-steps of;

detaching said semiconductor devices from said support substrate by removing said bonding medium while maintaining the state in which said semiconductor devices are connected with each other mechanically by said connection part;

bonding a rear side of said semiconductor devices, after being detached from said support substrate, upon a sticky medium; and

disconnecting said connection part

wherein said step (d) includes a sub-step for deforming said sticky medium to break said connection part, and

wherein said sticky medium is a sheet that is laterally expandable, and wherein said sub-step of deforming said sticky medium comprises the sub-steps of;

expanding said sheet to increase a distance between adjacent semiconductor devices to break said connection part; and

picking up said semiconductor devices.