Vertical MISFET devices

• US 5,920,088 A
• Filed: 06/17/1996
• Issued: 07/06/1999
• Est. Priority Date: 06/16/1995
• Status: Expired due to Term

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Inventors: Augusto, Carlos Jorge Ramiro Proenca
• Primary Examiner(s): Fahmy, Wael M.
• Application Number:
  US08/664,765
• Time in Patent Office: 1,114 Days
• Field of Search: 257/19, 257/192, 257/194, 257/329, 257/330, 257/331
• US Class Current: 257/192
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

The present invention relates to Silicon Germanium-based Vertical MISFET devices allowing smaller device size and exhibiting significant advantages over prior devices related to the reduction of drain induced barrier lowering and parasitic capacitance and permitting a higher integration density.

Claims

1. A PMOS type Vertical MISFET transistor composed of at least two semiconducting materials, comprising:

a drain layer with a first orientation and made of a highly p-type doped material;

a channel layer made of an undoped material and having said first orientation;

a source layer with said first orientation, said source layer comprising at least a double layer comprising an undoped or lowly p-type doped region, both made of a second material which has a valence band edge with a lower potential energy than valence band edge of said undoped material of the channel layer;

wherein said channel layer is positioned between said drain layer and said source layer and has an interface with said source layer, said interface has a band structure;

a gate overlapping at least partially said source layer, said channel layer and said drain layer with an insulating layer therebetween; and

a semiconductor heterojunction being formed between said source layer and said channel layer, and an undoped or lowly doped region being present in said source layer adjoining to said interface, said heterojunction and said lowly doped region achieving a bending of the band structure at said interface such that transistor action can be achieved through modulating voltage being applied on said gate.

2. The MISFET transistor of claim 1 wherein said highly p-type doped material of said drain layer is the same material as said channel layer.

3. The PMOS type MISFET transistor of claim 1 wherein:

a) said drain layer comprises a highly doped p++ layer; and

b) said source layer comprises at least a double layer comprising an undoped or lowly doped Si_1-x GE_x layer and a highly doped p++ SiGe layer.

4. The Vertical MISFET transistor of claim 3, wherein said highly doped p++ SiGe layer is graded.

5. The MISFET transistor of claim 3 wherein said undoped channel layer is silicon.

6. The MISFET transistor of claim 3, wherein the source layer is strained to a highly p-type doped layer.

7. The MISFET transistor of claim 6 wherein said highly p-type doped layer is Si.

8. The MISFET transistor of claim 7 wherein the drain layer comprises at least a highly p-type doped SiGe layer and a highly p-type doped Si₀.5 Ge₀.5 layer.

9. The Vertical MISFET transistor of claim 8, wherein said highly p-type doped SiGe layer is graded.

12. The Vertical MISFET transistor of claim 3 wherein:

a) the drain layer is made of a highly doped n++ material;

b) said channel layer is an undoped material; and

c) said source layer comprises at least a double layer comprising an undoped or lowly doped layer selected from the group consisting of Si_1-x-y Ge_x C_y and Si_1-y C_y layer, and a highly doped n++ layer selected from the group consisting of Si_1-x-y Ge_x C_y and Si_1-y C_y.

13. The Vertical MISFET transistor of claim 12 wherein said drain layer and said channel layer are silicon layers.

14. The Vertical MISFET transistor of claim 12, wherein the source layer is strained to a highly n-type doped Si layer.

10. A PMOS type Vertical MISFET transistor composed of at least two semiconducting materials, comprising:

a drain layer with a first orientation and made of a highly n-type doped material;

a channel layer made of an undoped material and having said first orientation;

a source layer with said first orientation, said source layer comprising at least a double layer comprising an undoped or lowly n-type doped region, both made of a second material which has a conduction band edge with a lower potential energy than conduction band edge of said undoped material of the channel layer;

wherein said channel layer is positioned between said drain layer and said source layer and has an interface with said source layer, said interface has a band structure;

a gate overlapping at least partially said source layer, said channel layer and said drain layer with an insulating layer therebetween; and

a semiconductor heterojunction being formed between said source layer and said channel layer, and an undoped or lowly doped region being present in said source layer adjoining to said interface, said heterojunction and said lowly doped region achieving a bending of the band structure at said interface such that transistor action can be achieved through modulating voltage being applied on said gate.

11. The Vertical MISFET transistor of claim 10 wherein said drain layer and said channel layer are the same material.

15. The Vertical MISFET transistor of claim 10 wherein:

a) the drain layer comprises a highly doped n++ layer;

b) the channel layer is an undoped layer; and

c) the source layer comprises at least a double layer comprising an undoped or lowly doped Si_1-y Ge_y layer, and a highly doped n++ SiGe layer.

16. The Vertical MISFET transistor of claim 15 wherein said drain layer and said channel layer are Ge layers.

17. The Vertical MISFET transistor of claim 15, wherein the source layer is strained to a highly n-type doped Si₀.5 Ge₀.5 layer.

18. The Vertical MISFET transistor of claim 17 wherein the drain layer comprises a highly n-type graded SiGe layer and a highly n-type doped Si₀.5 Ge₀.5 layer.

19. The Vertical MISFET transistor of claim 18, wherein said highly n-type doped SiGe layer is graded.