Vertical MISFET devices
First Claim
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1. A PMOS type Vertical MISFET transistor composed of at least two semiconducting materials, comprising:
- a drain layer with a first orientation and made of a highly p-type doped material;
a channel layer made of an undoped material and having said first orientation;
a source layer with said first orientation, said source layer comprising at least a double layer comprising an undoped or lowly p-type doped region, both made of a second material which has a valence band edge with a lower potential energy than valence band edge of said undoped material of the channel layer;
wherein said channel layer is positioned between said drain layer and said source layer and has an interface with said source layer, said interface has a band structure;
a gate overlapping at least partially said source layer, said channel layer and said drain layer with an insulating layer therebetween; and
a semiconductor heterojunction being formed between said source layer and said channel layer, and an undoped or lowly doped region being present in said source layer adjoining to said interface, said heterojunction and said lowly doped region achieving a bending of the band structure at said interface such that transistor action can be achieved through modulating voltage being applied on said gate.
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Abstract
The present invention relates to Silicon Germanium-based Vertical MISFET devices allowing smaller device size and exhibiting significant advantages over prior devices related to the reduction of drain induced barrier lowering and parasitic capacitance and permitting a higher integration density.
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Citations
19 Claims
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1. A PMOS type Vertical MISFET transistor composed of at least two semiconducting materials, comprising:
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a drain layer with a first orientation and made of a highly p-type doped material; a channel layer made of an undoped material and having said first orientation; a source layer with said first orientation, said source layer comprising at least a double layer comprising an undoped or lowly p-type doped region, both made of a second material which has a valence band edge with a lower potential energy than valence band edge of said undoped material of the channel layer; wherein said channel layer is positioned between said drain layer and said source layer and has an interface with said source layer, said interface has a band structure; a gate overlapping at least partially said source layer, said channel layer and said drain layer with an insulating layer therebetween; and a semiconductor heterojunction being formed between said source layer and said channel layer, and an undoped or lowly doped region being present in said source layer adjoining to said interface, said heterojunction and said lowly doped region achieving a bending of the band structure at said interface such that transistor action can be achieved through modulating voltage being applied on said gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14)
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10. A PMOS type Vertical MISFET transistor composed of at least two semiconducting materials, comprising:
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a drain layer with a first orientation and made of a highly n-type doped material; a channel layer made of an undoped material and having said first orientation; a source layer with said first orientation, said source layer comprising at least a double layer comprising an undoped or lowly n-type doped region, both made of a second material which has a conduction band edge with a lower potential energy than conduction band edge of said undoped material of the channel layer; wherein said channel layer is positioned between said drain layer and said source layer and has an interface with said source layer, said interface has a band structure; a gate overlapping at least partially said source layer, said channel layer and said drain layer with an insulating layer therebetween; and a semiconductor heterojunction being formed between said source layer and said channel layer, and an undoped or lowly doped region being present in said source layer adjoining to said interface, said heterojunction and said lowly doped region achieving a bending of the band structure at said interface such that transistor action can be achieved through modulating voltage being applied on said gate. - View Dependent Claims (11, 15, 16, 17, 18, 19)
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Specification