Reducing reverse short-channel effect with light dose of P with high dose of as in n-channel LDD

• US 5,920,104 A
• Filed: 09/03/1997
• Issued: 07/06/1999
• Est. Priority Date: 03/25/1996
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Nayak, Deepak Kumar, Heiler, Felicia, Rakkhit, Rajat
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/922,504
• Time in Patent Office: 671 Days
• Field of Search: 257/344, 257/408
• US Class Current: 257/408
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

Submicron nLDD CMOS logic devices with improved current drive and reduced reverse short-channel effects having heavily doped As and lightly doped P nLDD region.

Claims

1. A semiconductor device having a reduced reverse short-channel effect, comprising:

a semiconductor substrate of a first conductivity type;

a gate oxide film formed on said semiconductor substrate;

a gate electrode formed on said gate oxide film; and

source and drain regions of a second conductivity type formed in said substrate in self-alignment with said gate electrode with a channel region thereby defined in said substrate between said source and drain regions;

wherein

at least said drain region of said source and drain regions comprises a first region formed by a first implantation of a first impurity at a dosage of approximately 3×

10¹⁵ ions per cm², a second region formed by a second implantation of the first impurity at a dosage of approximately 4×

10¹⁴ ions per cm² and by a first implantation of a second impurity at a dosage of approximately 2×

10¹³ ions per cm², whereby the reverse short-channel effect is reduced.

2. The semiconductor device of claim 1 wherein said second region comprises a first portion and a second portion and wherein said second portion includes said first portion.

3. The semiconductor device of claim 2, wherein said first portion contains ions of said first impurity implanted at a dosage of approximately 4×

10¹⁴ ions per cm² and wherein said second portion contains ions of said second impurity implanted at a dosage of approximately 2×

10¹³ ions per cm².

4. The semiconductor device of claim 3, wherein said second portion of said second region is adjacent to an end of said channel region.

5. The semiconductor device of claim 2, wherein said first impurity is arsenic.

6. The semiconductor device of claim 5, wherein said second impurity is phosphorus.

7. The semiconductor device of claim 6, further comprising a sidewall spacer formed on each side of said gate electrode.