Parameterized cells for generating dense layouts of VLSI circuits

• US 5,920,486 A
• Filed: 08/16/1996
• Issued: 07/06/1999
• Est. Priority Date: 08/16/1996
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Beahm, Martin Emery, Joshi, Rajiv Vasant, Chappell, Terry Ivan
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/699,095
• Time in Patent Office: 1,054 Days
• Field of Search: 364/488-491, 364/578, 395/500
• US Class Current: 716/102
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

The invention provides a technique, given a netlist containing a description of the terminal connections and the length and width of each device in a circuit, for automatically producing a layout for each device in that circuit.

Claims

1. A method for automatically generating a layout of a VLSI circuit, comprising the computer implemented steps of:

inputting a data file describing the circuit;

computing one or more parameters of the layout;

responsive to the computation of one or more parameters, generating a substantially limitless number of shapes representing components of the circuit, said components include multifinger devices, shared devices, and tapered devices having technology dependent spacing;

placing the shapes in the appropriate configuration;

computing the shapes in the appropriate configuration;

if stacked devices are present in the circuit;

computing the shape and position of the stacked devices;

computing an overlay position for the stacked devices;

generating wiring connections and configuration to connect the devices in the layout in the desired fashion; and

outputting a layout of the circuit.

2. The method of claim 1, wherein the circuit is represented at the gate level in the data file.

3. The method of claim 1, wherein the circuit is represented at the device level in the data file.

4. The method of claim 3, wherein the device level data includes the width (W), length (L) and number of fingers (M) of each device.

5. The method of claim 1, wherein the device level data further comprises the width (W) and length (L) of each device, and wherein the number of fingers of each device (M) is computed automatically.

6. The method of claim 1, further comprising inputting data describing technology rules associated with a technology in which the layout will be generated.

7. The method of claim 1, wherein the step of placing the shapes in an appropriate configuration is performed automatically.

8. The method of claim 7, wherein the shapes are placed automatically based upon circuit timing information.

9. The method of claim 7, wherein the shapes are placed automatically such that circuit wiring delay is minimized.

10. The method of claim 1, wherein the step of placing the shapes is performed by a user of the method.

11. The method of claim 1, further comprising automatically checking the layout for technology design rule violations.

12. The method of claim 1, further comprising cross-checking the layout against the data file describing the circuit to determine whether the entire circuit has been represented in the layout.

13. The method of claim 1, further comprising modifying the wiring connections and configuration in response to user input.

14. The method of claim 1, wherein the step of generating the wiring connections and configuration to connect the devices in the layout in the desired fashion is performed automatically.

15. The method of claim 1, further comprising compacting the layout to occupy as small an area as possible prior to outputting the layout.

16. The method of claim 1, wherein the output representing the layout is in GL1 format.

17. The method of claim 1, further comprising interactively checking the layout during placement.

18. The method of claim 1, further comprising continuously tuning device sizes to achieve performance and area criteria.

19. The method of claim 1, further comprising migrating the layout from one technology to a second technology.

20. A method for automatically generating a layout of a VLSI circuit, comprising the computer implemented steps of:

inputting a data file containing a gate level description of the circuit;

generating a substantially limitless number of shapes, programmable library book set containing programmable layouts for each type of gate in the data file;

providing ground rule and layer information for the technology in which the circuit is to be fabricated;

inputting desired row height, area, vdd and ground information for the circuit;

using the programmable layout in the programmable library book, the ground rule and layer information and the input information, generating a second library representing all cells in the circuit;

generating schematic and symbolic representations of the circuit using the contents of the second library;

placing symbols representing the elements of the circuit in an appropriate configuration wherein said configuration can be user modifiable or placed automatically; and

outputting a layout of the circuit containing the appropriately configured shapes.

21. A method for automatically generating a layout of VLSI circuit, comprising the computer implemented steps of:

inputting a data file describing the circuit, the elements of the circuit being represented at the device level, the device level data comprising the width (W), length (L) and number of fingers (M) of each device;

inputting data describing technology rules associated with a technology in which the layout will be generated;

computing one or more parameters of the layout;

responsive to the computation of one or more parameters, generating a substantially limitless number of shapes, said shapes representing components of the circuit;

automatically placing the shapes in a appropriate configuration;

automatically checking the layout for technology design rule violations;

cross-checking the layout against the data file describing the circuit to determine whether the entire circuit has been represented in the layout;

if stacked devices are present in the circuit;

computing the shape and position of the stacked devices;

computing an overlay position for the stacked devices;

generating the wiring connections and configuration to connect the devices in the layout in the desired fashion;

modifying the wiring connections and configuration in response to user input for reducing wiring parasites;

compacting the layout to occupy as small an area as possible prior to outputting the layout; and

outputting a layout of the circuit.