Apparatus for amplifying a signal using a digital processor

• US 5,920,596 A
• Filed: 09/22/1997
• Issued: 07/06/1999
• Est. Priority Date: 01/31/1995
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Sigmon, Bernard E., Pan, Shaowei, Laird, Kevin M., Wang, Shay-Ping T., Ma, Stephen Chih-Hung
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Tran, Khai
• Application Number:
  US08/935,212
• Time in Patent Office: 652 Days
• Field of Search: 375/238, 375/353, 375/239, 375/308, 375/316, 375/318, 375/319, 375/297, 330/136, 330/285, 330/297, 330/2, 330/10, 330/207 A, 330/251, 370/212, 364/748.5
• US Class Current: 375/238
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06

Abstract

An apparatus for amplifying a signal that includes a digital processor (12) producing a first digital signal (20) and a second digital signal (22), a pulse width modulator (32) receiving the first digital signal (20) and producing a pulse width modulated signal, an amplitude restoration module (37) responsive to the pulse width modulator (32), the amplitude restoration module (37) producing an amplitude envelope signal, a frequency upconverter (16) receiving the second digital signal (22) and producing a frequency modulated signal, and a power amplifier (18) responsive to the frequency upconverter and the amplitude restoration module (37). The power amplifier receives the frequency modulated signal and the amplitude envelope signal and produces an amplified output signal.

Claims

1. An apparatus for amplifying a signal, the apparatus comprising:

a digital processor including a digital logarithm converter, a shifter, and a digital inverse logarithm converter wherein the digital logarithm converter, the shifter, and the digital inverse logarithm converter effect an exponentiation operation, the digital processor producing a first digital signal and a second digital signal;

a pulse width modulator receiving the first digital signal and producing a pulse width modulated signal;

an amplitude restoration module responsive to the pulse width modulator, the amplitude restoration module producing an amplitude envelope signal;

a frequency upconverter receiving the second digital signal and producing a frequency modulated signal; and

a power amplifier responsive to the frequency upconverter and the amplitude restoration module, the power amplifier receiving the frequency modulated signal and the amplitude envelope signal and producing an amplified output signal.

2. The apparatus of claim 1, wherein the digital processor receives a baseband digital input signal having a first component and a second component and wherein the first digital signal is derived from a square of the first component and a square of the second component.

3. The apparatus of claim 2, wherein the first component is an inphase component and the second phase is a quadrature phase component.

4. The apparatus of claim 1, wherein the second signal is a time delayed signal.

5. The apparatus of claim 1, wherein the frequency modulated signal is amplitude limited.

6. The apparatus of claim 1, wherein the power amplifier comprises a class E type power amplifier.

7. The apparatus of claim 1, wherein the pulse width modulator comprises a digital pulse width modulator that is integrated into the digital processor.

8. The apparatus of claim 1, wherein the digital processor comprises a polynomial processor.

9. The apparatus of claim 1, wherein the digital processor includes a pre-distortion module.

10. The apparatus of claim 1, wherein the digital processor includes at least one of a phase lock loop and a delay lock loop.

11. The apparatus of claim 1, wherein the digital processor includes a modulator and wherein the second digital signal is an amplitude limited frequency modulated signal.

12. The apparatus of claim 1, wherein the digital processor approximates a sinusoidal function using a polynomial to produce the second digital signal.

13. The apparatus of claim 1, wherein the digital processor comprises a parallel processing device including a logarithm converter, combinatorial logic, and an inverse logarithm converter.

14. The apparatus of claim 1, wherein the digital processor comprises a summation of squares generator, a predistortion module responsive to the summation of squares generator, a cosine approximation unit responsive to the summation of squares generator, a phase lock loop, a delay lock look responsive to the phase lock loop, and a pulse width modulator responsive to the predistortion module and the delay lock loop.

15. An apparatus for amplifying a signal, the apparatus comprising:

a digital processor including a digital logarithm converter, a shifter, and a digital inverse logarithm converter wherein the digital logarithm converter, the shifter, and the digital inverse logarithm converter effect an exponentiation operation, the digital processor having a first digital output and a second digital output;

an amplitude restoration module responsive to the first output of the digital processor, the amplitude restoration module having an amplitude signal output;

a frequency upconverter responsive to the second digital output of the digital processor and having a frequency modulated output; and

a power amplifier having a first input responsive to the frequency modulated output of the frequency upconverter and a second input responsive to the amplitude signal output of the amplitude restoration module, the power amplifier further comprising an amplifier output.

16. The apparatus of claim 15, wherein the digital processor includes a logarithm converter, a bit shifter responsive to the logarithm converter, and an inverse logarithm converter responsive to the shifter.

17. The apparatus of claim 15, wherein the digital processor includes a predistortion estimation module and a pulse width modulator.

18. The apparatus of claim 15, wherein the digital processor includes a plurality of logarithm converters and a phase lock loop.