Serial port having only a single terminal for information transfer to and from an integrated circuit

• US 5,920,708 A
• Filed: 01/26/1996
• Issued: 07/06/1999
• Est. Priority Date: 11/09/1994
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Burns, Christopher, Gates, Stillman F.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): TZENG, FRED
• Application Number:
  US08/592,800
• Time in Patent Office: 1,257 Days
• Field of Search: 370/257, 395/822, 395/250, 395/310, 395/309
• US Class Current: 710/305
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation

Abstract

A host adapter integrated circuit that contains data transfer modules has a serial port that uses a single serial port pin to communicate with a slave serial port input-output integrated circuit that interfaces to various resources that are included in a support circuit. The serial port forms a packet from each byte of information to be transferred from a module to the slave device by adding a start bit before the byte, followed by a parity bit at the end of the byte and followed by a stop bit. After transmitting the packet, the serial port waits for an acknowledge packet from the slave serial port input-output integrated circuit, for example for two clock cycles after transmission of the packet. For synchronous operation, a common oscillator drives the clock signal on the slave serial port input-output integrated circuit and host adapter integrated circuit. The serial port pin in the host adapter integrated circuit is connected to a shifter circuit in the serial port that serially clocks data from the serial port pin and passes the data parallelly to a bus in the host adapter integrated circuit and vice versa.

Claims

1. A host adapter integrated circuit comprising:

a first plurality of pins couplable to a first bus;

a second plurality of pins couplable to a second bus;

a data transfer circuit connected to said first and second pluralities of pins;

wherein said data transfer circuit transfers information between said first and second pluralities of pins; and

a serial port coupled to said data transfer circuit, and said serial port having only one pin, said pin being a bidirectional pin, wherein said serial port serially drives a plurality of signals on said pin in response to receipt of said plurality of signals from said data transfer circuit, and serially receives another plurality of signals from said pin;

wherein said serial port further comprises a plurality of serially coupled storage elements;

wherein data from said serially coupled storage elements are serially provided to said pin in response to a first signal; and

further wherein data from said pin are serially stored in said serially coupled storage elements in response to a second signal.

2. The host adapter integrated circuit of claim 1 wherein said first bus is an input and output bus connected to a peripheral device and said second bus is a system bus connected to a host processor;

and further wherein said serially connected storage element have a parallel input terminals wherein data from said second bus are provided to said parallel input terminals and are latched in parallel in said serially coupled storage elements in response to a third edge in said buffered clock signal.

3. The host adapter integrated circuit of claim 2 wherein data from said serially coupled storage elements are written on said system bus in parallel in response to a read strobe.

4. The host adapter integrated circuit of claim 2 further comprising:

a hold register coupled to said serially coupled storage elements wherein upon transfer of data from said serially coupled storage elements to said hold register, said data is provided to a plurality of received data terminals in response to a fourth edge in said buffered clock signal.

5. The host adapter integrated circuit of claim 1, wherein:

said serial port waits for at least a predetermined time period after power-on reset for an initialization signal on said pin prior to driving said plurality of signals on said pin.

6. An apparatus comprising:

a first integrated circuit having a first serial port wherein said first serial port has only a first bidirectional pin;

a second integrated circuit having a second serial port wherein said second serial port has only a second bidirectional pin; and

a bidirectional line connecting said first bidirectional pin to said second bidirectional pin;

wherein said second integrated circuit generates an acknowledge packet on said second bidirectional pin in response to a command packet from said first integrated circuit on said first bidirectional pin.

7. The apparatus of claim 6 further comprising:

a system bus coupled to said first serial port; and

an oscillator; and

farther wherein

said first integrated circuit further comprises a clock pin coupled to said oscillator and said first integrated circuit generates a buffered clock signal in response to a signal on said clock pin; and

said second integrated circuit further comprises a clock pin coupled to said oscillator.

8. The apparatus of claim 7 wherein said first serial port further comprises:

a command generator circuit having a serial port input-output bus coupled to said system bus, and a parallel output bus wherein in response to a signal on said serial input-output bus, said command generator circuit drives a command on said parallel bus.

9. The apparatus of claim 8 wherein said command comprises a byte of information.

10. The apparatus of claim 8 wherein said command includes a plurality of command bits.

11. The apparatus of claim 10 wherein said command includes a plurality of data bits.

12. The apparatus of claim 10 wherein said serial port input-output bus further comprises a plurality of serial port command lines.

13. The apparatus of claim 8 wherein said first serial port further comprises:

a converter circuit connected to said parallel bus, and said converter circuit having a serial data terminal wherein said converter circuit formats said command received on said parallel bus into a packet and serially transmits said packet on said serial data output terminal.

14. The apparatus of claim 13 wherein said packet includes a start bit.

15. The apparatus of claim 13 wherein said packet includes a stop bit.

16. The apparatus of claim 13 wherein said packet includes a parity bit.

17. The apparatus of claim 13 wherein said first serial port further comprises:

a line controller circuit connected to said serial data output terminal of said converter circuit and coupled to said first bidirectional pin wherein said line controller circuit transfers data from said serial data output terminal of said converter circuit to said first bidirectional terminal.

18. A method for serially transferring information on a bidirectional line between a first device and a second device, the method comprising:

(1) in said first device;

waiting for at least a predetermined time period after a power-on reset signal for an initialization signal on said bidirectional line; and

(2) in said second device;

transmitting said initialization signal on said bidirectional line in response to said power-on reset signal; and

driving a signal on said bidirectional line, subsequent to said initialization signal, only in response to a signal from said first device on said bidirectional line.

19. The method of claim 18 wherein said second device drives an acknowledge signal on said bidirectional line within a predetermined time of receiving said signal from said first device.

20. The method of claim 19 further comprising:

waiting by said first device for completion of said acknowledge signal from said second device before driving another signal on said bidirectional line by said first device.

21. The method of claim 18 wherein each of said devices is an integrated circuit, said method further comprising:

driving a common clock signal to each of said devices.

22. An apparatus comprising:

a first plurality of pins couplable to a first bus;

a circuit connected to said first plurality of pins, wherein said circuit transfers information to and from said first plurality of pins; and

a serial port coupled to said circuit, and said serial port having only one pin, said pin being a bidirectional pin for receipt and transmission of signals, wherein;

said serial port serially drives a plurality of signals on said pin in response to receipt of said plurality of signals from said circuit; and

said serial port waits for at least a predetermined time period after power-on reset for an initialization signal on said pin prior to driving said plurality of signals on said pin.

23. The apparatus of claim 22 further comprising:

a clock pin;

wherein said circuit includes a plurality of modules, and a first module in said plurality of modules receives a clock signal from said clock pin and supplies a buffered clock signal to the other modules in said plurality of modules.