Emulation system having multiple emulator clock cycles per emulated clock cycle

• US 5,920,712 A
• Filed: 11/12/1996
• Issued: 07/06/1999
• Est. Priority Date: 05/13/1994
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Kuijsten, Han
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): MOHAMED, AYNI Y
• Application Number:
  US08/748,154
• Time in Patent Office: 966 Days
• Field of Search: 395/500, 371/16.2
• US Class Current: 703/23
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Claims