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Method and apparatus for transferring signals between multiple clock timing domains

  • US 5,923,193 A
  • Filed: 12/11/1996
  • Issued: 07/13/1999
  • Est. Priority Date: 12/11/1996
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising:

  • electronic for transferring a digital data signal along a digital data signal between different clock timing domains;

    said different clock timing domains comprising a first clock timing domain and a second clock timing domain;

    a common high frequency source clock coupled to a clock generator circuit providing a first and a second clock timing signal;

    said clock timing signal having a relatively fixed phase;

    said second clock timing signal having a relatively varying phase;

    wherein said first and second clock timing domains receive said first and second clock timing signals, respectively;

    said clock generator circuit further including delay elements for providing said second and first clock timing signals so that the second and first clock timing signals are respectively staggered for only a relatively short time compared with a given cycle of the common high frequency source clock;

    said digital data signal path further including a data value retention element coupled so as to transfer said digital data signal between said second and first clock timing domains so as to delay the transfer of said digital data signal between said second and first clock timing domains at selected times.

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