SRAM with ROM functionality

• US 5,923,582 A
• Filed: 06/03/1997
• Issued: 07/13/1999
• Est. Priority Date: 06/03/1997
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Voss, Peter H.
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US08/868,062
• Time in Patent Office: 770 Days
• Field of Search: 365/154, 365/156, 365/104
• US Class Current: 365/154
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 17/08 using semiconductor devices, e.g. bipolar elements G11C17/06, G11C17/14 take precedence
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A memory device including a first block of random access memory (RAM) cells having preprogrammed states, a second block of random access memory cells, and a select circuit configured to reset the first block of RAM cells to their preprogrammed states. When the first block of memory cells are reset to their preprogrammed states, the first block of memory cells may function as ROM memory cells that may be accessed at RAM speeds. The first block of RAM cells may not require additional nonvolatile circuitry in order to perform the ROM function; rather, the first block of RAM cells may each be configured to operate as both a volatile and nonvolatile memory cell using the same cell structure. For one embodiment, the select circuit alters the power applied to the first block of RAM cells to cause these RAM cells to perform a ROM function. Since, the first block of RAM cells may store RAM data when the device operates in RAM mode, and may store preprogrammed ROM data when reset by the select circuit, the first block of RAM cells may have a storage capacity that is greater than the number of RAM cells in the first block.

Claims

1. A circuit comprising:

a plurality of memory cells configured to store both random access memory (RAM) data and read only memory (ROM) data; and

a select circuit coupled to the plurality of memory cells and configured to enable access to the RAM data or ROM data in response to an address signal.

2. The circuit of claim 1, wherein the select circuit alters power supplied to the first plurality of RAM cells in response to the address signal.

3. The circuit of claim 1, wherein one of the plurality of RAM cells comprises a first PMOS transistor having a first length and a second PMOS transistor having a second length different than the first length.

4. The circuit of claim 1, wherein the select circuits enable access to the RAM data when the address signal is in a first state, and wherein the select circuit enables access to the ROM data when the address signal is in a second state.

5. The circuit of claim 1, wherein the first plurality of RAM cells are static RAM cells.

6. The circuit of claim 1, wherein the first plurality of RAM cells are dynamic RAM cells.

7. The circuit of claim 1, wherein the select circuit is configured to enable access to the ROM data in response to the address signal by cycling power supplied to the memory cells from a first voltage to a second voltage, and from the second voltage to the first voltage, wherein the second voltage is less than the first voltage.

8. The circuit of claim 7, wherein one of the memory cells comprises a first PMOS transistor having a first length and a second PMOS transistor having a second length different than the first length.

9. The circuit of claim 7, wherein one of the memory cells is a static RAM cell.

10. The circuit of claim 7, wherein one of the memory cells is a dynamic RAM cell.

11. The circuit of claim 1, wherein one of the memory cells comprises a dynamic random access memory (DRAM) cell.

12. The circuit of claim 11, further comprising:

a word line coupled to the DRAM cell;

a first bit line coupled to the DRAM cell and the select circuit;

a second bit line coupled to the DRAM cell and the select circuit; and

a pre-charge circuit coupled to the first and second bit lines.

13. The circuit of claim 12, wherein the select circuit provides the same logic levels to the first and second bit lines, and subsequently couples the first and second bit lines to the pre-charge circuit to enable access to a bit of the ROM data in the DRAM cell.

14. The circuit of claim 12, wherein the DRAM cell comprises:

a pair of cross-coupled transistors; and

a pair of pass transistors coupling the cross-coupled transistors to the first and second bit lines.

16. The method of claim 12, wherein, the RAM cell is coupled to a pair of bit lines, and the method further comprises the step of driving the bit lines to a same voltage while the power applied to the RAM cell is at the second voltage.

15. A method of retrieving preprogrammed data from a random access memory (RAM) cell, comprising the step of:

cycling power applied to the RAM cell from a first voltage to a second voltage, and from the second voltage to the first voltage, wherein the second voltage is less than the first voltage, wherein the cycling step occurs in response to an address signal.

17. A memory circuit comprising:

a random access memory (RAM) address space implemented in a plurality of memory cells;

a read only memory (ROM) address space implemented in the plurality of memory cells; and

a select circuit configured to address the RAM address space or the ROM address space in response to an address signal.