Memory circuit

• US 5,923,591 A
• Filed: 04/05/1998
• Issued: 07/13/1999
• Est. Priority Date: 09/24/1985
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kuwabara, Tadashi, Kimura, Koichi, Ogura, Toshihiko, Enomoto, Hiromichi, Aotsu, Hiroaki, Kyoda, Tadashi, Ikegami, Mitsuru
• Primary Examiner(s): Fears, Terrell W
• Application Number:
  US09/055,327
• Time in Patent Office: 464 Days
• Field of Search: 365/189.01, 365/189.03, 365/200
• US Class Current: 365/189.03
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

Claims

1. A memory device formed on an IC chip, comprising:

dynamic random access memory means for effecting data read write operations, and having input means, output means, and a plurality of storage locations for storing data;

first and second data terminals, said terminals being formed on the IC chip to receive data from an external side of the IC chip, said first data terminal being to be connected to data bus, and said second data terminal being to be connected to lines other than said data bus; and

control means having an output connected to said input means of said dynamic random access memory means, a first data input connected to said first data terminal to receive first data, a second input connected to receive second data read from a selected part of said storage locations via said output means of said dynamic random access memory means, a third data input connected to said second data terminal to receive a function mode signal, and operation means for executing operations between said first data provided from said first data input and said second data provided from said second input, said operation means including function setting means responsive to said function mode signal for setting a function indicated by said function mode signal prior to receipt of said first data, wherein said second data is read out of said selected part of said storage locations, the operation corresponding to the function set by said function setting means is executed for said first and second data, and the result of said execution is written into said selected part of said storage locations via said input means of said dynamic random access memory means during one memory cycle of said dynamic random access memory means.

2. A memory device according to claim 1, wherein said operations executed by said operation means are logic operations between said first data and said second data.

3. A memory device according to claim 1, wherein said operations executed by said operation means are arithmetic operations between said first data and said second data.

4. A memory device according to claim 2, wherein one of said logic operations is an operation to pass said first data as said result to said input means of said dynamic random access memory means.

5. A memory device according to claim 1, wherein said dynamic random access memory means is used for storing graphic data as the data.

6. A memory device with operation function, formed on one chip as an integrated device, comprising:

dynamic random access memory means for storing data;

first and second data terminals, said terminals being formed on the chip in order to receive data from an external side of the integrated device, said first data terminal being to be connected to data bus, and said second data terminal to be connected to lines other than said data bus; and

means for executing an operation between data provided through said first data terminal and data read from said dynamic random access memory means, the result of said operation being stored in said dynamic random access memory means, including function setting means responsive to a function mode signal provided through said second data terminal for setting a function indicated by said function mode signal prior to receipt of data through said first data terminal, whereby the operation of said executing means is preset in accordance with the function set by said function setting means prior to receipt of said data through said first data terminal, and wherein the reading out of data from said dynamic random access memory means, the execution of said operation on said data by said execution means and the storing of the result of the execution is effected during one memory cycle of said random access memory means.

7. A memory device according to claim 6, wherein said operations executed by said execution means are logic operations between said data provided through said first data terminal and said data read from said dynamic random access memory means.

8. A memory device according to claim 6, wherein said operations executed by said execution means are arithmetic operations between said data provided through said first data terminal and said data read from said dynamic access memory means.

9. A memory device according to claim 6, wherein one of said operations executed by said executing means is an operation to pass said data provided through said first data terminal as said result to said dynamic random access memory means.

10. A memory device according to claim 6, wherein said dynamic random access memory means stores graphic data as the data.

11. A memory device formed on an IC chip, comprising:

dynamic random access memory means for effecting data read and write operations, and having input means, output means, and a plurality of storage locations for storing data;

first and second data terminals, said terminals being formed on the IC chip to receive data from an external side of the IC chip, said first data terminal being to be connected to data bus, and said second data terminal being to be connected to address bus; and

control means having an output connected to said input means of said dynamic random access memory means, a first data input connected to said first data terminal to receive first data, a second input connected to receive second data read from a selected part of said storage locations via said output means of said dynamic random access memory means, a third data input connected to said second data terminal to receive a function mode signal, and operation means for executing operations between said first data provided from said first data input and said second data provided from said second input, said operation means including function setting means responsive to said function mode signal for setting a function indicated by said function mode signal prior to receipt of said first data, wherein said second data is read out of said selected part of said storage locations, the operation corresponding to the function set by said function setting means is executed for said first and second data, and the result of said execution is written into said selected part of said storage locations via said input means of said dynamic random access memory means during one memory cycle of said dynamic random access memory means.

12. A memory device according to claim 11, wherein said operations executed by said operation means are logic operations between said first data and said second data.

13. A memory device according to claim 11, wherein said operations executed by said operation means are arithmetic operations between said first data and said second data.

14. A memory device according to claim 12, wherein one of said logic operations is an operation to pass said first data as said result to said input means of said dynamic random access memory means.

15. A memory device according to claim 11, wherein said dynamic random access memory means is used for storing graphic data as the data.

16. A memory device with operation function, formed on one chip as an integrated device, comprising:

dynamic random access memory means for storing data;

first and second data terminals, said terminals being formed on the chip in order to receive data from an external side of the integrated device, said first data terminal being to be connected to data bus, and said second data terminal to be connected to address bus; and

means for executing an operation between data provided through said first data terminal and data read from said dynamic random access memory means, the result of said operation being stored in said dynamic random access memory means, including function setting means responsive to a function mode signal provided through said second data terminal for setting a function indicated by said function mode signal prior to receipt of data through said first data terminal, whereby the operation of said executing means is preset in accordance with the function set by said function setting means prior to receipt of said data through said first data terminal, and wherein the reading out of data from said dynamic random access memory means, the execution of said operation on said data by said executing means and the storing of the result of the execution is effected during one memory cycle of said random access memory means.

17. A memory device according to claim 16, wherein said operations executed by said execution means are logic operations between said data provided through said first data terminal and said data read from said dynamic random access memory means.

18. A memory device according to claim 16, wherein said operations executed by said execution means are arithmetic operations between said data provided through said first data terminal and said data read from said dynamic access memory means.

19. A memory device according to claim 16, wherein one of said operations executed by said executing means is an operation to pass said data provided through said first data terminal as said result to said dynamic random access memory means.

20. A memory device according to claim 16, wherein said dynamic random access memory means stores graphic data as the data.

21. A memory device on an IC chip responsive to an access from an external side of the IC chip, comprising:

dynamic memory means for effecting data read and write operations and having a plurality of memory locations;

a first path connected to said dynamic memory means for transferring data read out from one of said memory locations designated by an access address provided from the external side during a first duration of one memory cycle of said dynamic memory means;

control means having output means, first data input means connected to receive data provided via a data bus from the external side, second data input means connected to said first path for receiving said data read from said dynamic memory means, third data input means connected to receive a function mode signal supplied via address but from the external side prior to said first duration, and operation means for executing one of a plurality of operations selected in response to said function mode signal between said data received by said first data input means and said data received by said second data input means during a second duration of said one memory cycle following said first duration; and

a second path connecting said output means of said control means to said memory means for transferring a result of the execution of said selected operation, said result being stored in said designated location of said memory means during a third duration of said one memory cycle following said second duration.

22. A memory device according to claim 21, wherein said operation means repeats said selected operation within a plurality of memory cycles after receiving said function mode signal.

23. A memory device according to claim 21, wherein said operations are logic operations between said data received by said first data input means and said data received by said second data input means.

24. A memory device according to claim 21, wherein said operations are arithmetic operations between said data received by said first data input means and said data received by second data input means.

25. A memory device according to claim 21, wherein said selected operation is an operation to pass said data received by said first data input means.

26. A memory device on an IC chip having a data terminal, an address terminal, and a control terminal, comprising:

a memory element having a plurality of storage locations for reading, writing and storing data from, to and in said storage locations in response to address signals supplied through said address terminal and control signals supplied through said control terminal;

an operation means for operating on read data read out from said memory element and first data supplied through said data terminal in accordance with an operation mode signal and outputting result data; and

an operation mode setting means for setting said operation mode signal of said operation means with receiving said operation mode signal supplied through said address terminal.

27. A memory device on an IC chip according to claim 26, wherein said operation mode setting means receives said operation mode signal through said address terminal at another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

28. A memory device on an IC chip according to claim 26, wherein said result data outputted from said operation means is written to said memory element.

29. A memory device on an IC chip according to claim 26, wherein said address signals supplied through said address terminal to said memory element includes row address signals and column address signals.

30. A memory device on an IC chip according to claim 26, wherein said memory element stores graphic data as said data.

31. A memory device on an IC chip according to claim 26, wherein one of said control signals supplied through said control terminal is a decoded signal produced by decoding said address signals.

32. A memory device on an IC chip according to claim 26, wherein said operation means executes logical operations to said read data and said first data.

33. A memory device on an IC chip according to claim 32, wherein one of said logical operations is an operation to pass said first data as said result data to said memory element.

34. A memory device on an IC chip according to claim 26, wherein said operation means executes arithmetic operations to said read data and said first data.

35. A memory device on an IC chip according to claim 26, wherein said operation mode setting means receives said operation mode signal as lower bits of said address signals through said address terminal.

36. A memory device on an IC chip according to claim 26, wherein said memory element has a serial output port for outputting said data in serial.

37. A memory device on an IC chip having a data terminal, an address terminal, and a control terminal, comprising:

a memory element having a plurality of storage locations for reading, writing, and storing data from, to, and in said storage locations in response to address signals supplied through said address terminal and control signals supplied through said control terminal;

an operation means for operating on read data read out from said memory element and first data supplied through said data terminal to output result data in accordance with an operation mode signal; and

an operation mode setting means for receiving said operation mode signal supplied through said address terminal, and setting said operation mode signal to said operation means, said operation mode setting means including a plurality of operation mode register means respectively storing said operation mode signal and a first selector means for selecting one of a plurality of said operation mode register means to supply said operation mode signal to said operation means.

38. A memory device on an IC chip according to claim 37, wherein said operation mode setting means receives said operation mode signal through said address terminal at another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

39. A memory device on an IC chip according to claim 37, wherein said result data outputted from said operation means is written to said memory element.

40. A memory device on an IC chip according to claim 37, wherein said address signals supplied through said address terminal to said memory element includes row address signals and column address signals.

41. A memory device on an IC chip according to claim 37, wherein said memory element is used for storing graphic data as said data.

42. A memory device on an IC chip according to claim 37, wherein one of said control signals supplied through said control terminal is a decoded signal produced by decoding said address signals.

43. A memory device on an IC chip according to claim 37, wherein said operation means executes logical operations to said read data and said first data.

44. A memory device on an IC chip according to claim 43, wherein one of said logical operations is an operation to pass said first data as said result data to said memory element.

45. A memory device on an IC chip according to claim 37, wherein said operation mode setting means receives said operation mode signal as lower bits of said address signals through said address terminal.

46. A memory device on an IC chip according to claim 37, wherein said first selecting means selects said one of said operation mode register means in response to said control signals provided through said control terminal.

47. A memory device on an IC chip according to claim 37, wherein said memory element has a serial output port for outputting said data in serial.

48. A memory device on an IC chip having a data terminal, an address terminal, and a control terminal, comprising:

a memory element for reading, writing and storing data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and control signals supplied through said control terminal;

an operation means for operating on read data read out from said memory element and first data supplied through said data terminal in accordance with an operation mode signal and outputting result data;

an operation mode setting means for setting said operation mode signal with receiving said operation mode signal supplied through said address terminal; and

a write control means for outputting a write control signal in a bit unit to said memory element in accordance with second data supplied through said data terminal.

49. A memory device on an IC chip according to claim 48, wherein said operation mode setting means receives said operation mode signal through said address terminal at another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

50. A memory device on an IC chip according to claim 48, wherein said memory element is used for storing said result data outputted from said operation means.

51. A memory device on an IC chip according to claim 48, wherein said address signals supplied through said address terminal to said memory element includes row address signals and column address signals.

52. A memory device on an IC chip according to claim 48, wherein one of said control signals supplied through said control terminal is a decoded signal produced by decoding said address signals.

53. A memory device on an IC chip according to claim 48, wherein said operation means executes logical operations to said read data and said first data.

54. A memory device on an IC chip according to claim 53, wherein one of said logical operations is an operation to pass said first data as said result data to said memory element.

55. A memory device on an IC chip according to claim 48, wherein said operation mode setting means receives said operation mode signal as lower bits of said address signals through said address terminal.

56. A memory device on an IC chip according to claim 48, wherein said write control means receives said second data supplied through said data terminal in response to another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

57. A memory device on an IC chip according to claim 48, wherein said operation mode setting means and said write control means respectively receive said operation mode signal through said address terminal and said second data supplied through said data terminal in response to another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

58. A memory device on an IC chip according to claim 48, wherein said memory element has a serial output port for outputting said data in serial.

59. A memory device on an IC chip having a data terminal, an address terminal, and a control terminal, comprising:

a memory element for reading, writing, and storing data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and control signals supplied through said control terminal;

an operation means for operating on read data read out from said memory element and first data supplied through said data terminal to output result data in accordance with an operation mode control signal;

an operation mode setting means for receiving said operation mode control signal supplied through said address terminal, and setting said operation mode control signal to said operation means, said operation mode setting means including a plurality of operation mode register means respectively storing said operation mode control signal and a first selector means for selecting one of a plurality of said operation mode register means to supply said operation mode control signal to said operation means; and

a write control means for outputting a write control signal in a bit unit to said memory element in accordance with second data supplied from said data terminal, said write control means including a plurality of write control register means respectively storing said write control signal and a second selector means for selecting one of said write control register means to supply said write control signal to said memory element.

60. A memory device on an IC chip according to claim 59, wherein said operation mode setting means receives said operation mode control signal through said address terminal at another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

61. A memory device on an IC chip according to claim 59, wherein said memory element is used for storing said result data outputted from said operation means in accordance with said second data supplied from said write control means.

62. A memory device on an IC chip according to claim 59, wherein said address signals supplied through said address terminal to said memory element includes row address signals and column address signals.

63. A memory device on an IC chip according to claim 59, wherein said memory element stores graphic data as said data.

64. A memory device on an IC chip according to claim 59, wherein said operation means executes logical operations to said read data and said first data.

65. A memory device on an IC chip according to claim 64, wherein one of said logical operations is an operation to pass said first data as result data as to said memory element.

66. A memory device on an IC chip according to claim 59, wherein said operation mode setting means receives said operation mode control signal as lower bits of said address signals through said address terminal.

67. A memory device on an IC chip according to claim 59, wherein said first selector means selects said one of said operation mode register means in response to said control signals provided through said control terminal.

68. A memory device on an IC chip according to claim 59, wherein said write control means receives said second data supplied through said data terminal in response to another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

69. A memory device on an IC chip according to claim 59, wherein said operation mode setting means and said write control means respectively receive said operation mode signal through said address terminal and said second data supplied through said data terminal in response to another combination of said control signals different from a combination of said control signals for a normal memory access to said memory element.

70. A memory device on an IC chip according to claim 59, wherein said second selector means selects said one of said write control means in response to said control signals provided through said control terminal.

71. A memory device on an IC chip according to claim 59, wherein said first selector means and second selector means respectively select said one of said operation mode register means and said one of said write control register means in response to said control signals provided through said control terminal.

72. A memory device on an IC chip according to claim 59, wherein said memory element has a serial output port for outputting said data in serial.

73. A one chip semiconductor integrated circuit device comprising:

a memory unit including a plurality of semiconductor memory elements;

a first terminal which is supplied with operation designation signals and an address signal, said operation designation signals arbitrarily designating one of a plurality of operations;

a control unit which is coupled to said memory elements and said first terminal and which sets a plurality of bits of said memory elements of said memory unit into a predetermined logic level according to a selected predetermined operation designated by said operation designation signals, said predetermined logic level being data irrespective of data provided by an external device; and

a second terminal coupled to said control unit;

wherein said operation designation signals are control command data bits which are supplied from said first terminal;

address signal is used to write into said memory unit write data in response to a data setting control signal, said data setting control signal being supplied from said second terminal;

wherein during a mode designation operation, before a bits setting operation, said operation designation signals being said control command data bits are supplied from said first terminal, said mode designation operation is carried out in response to another data setting control signal which is also supplied from said second terminal; and

wherein during said bits setting operation said control unit sets said plurality of bits of said memory elements of said memory unit into said predetermined logic level according to said selected predetermined operation designated by said operation designation signals being said control command data bits which are supplied from said first terminal during said mode designation operation.

74. A one chip semiconductor integrated circuit device according to claim 73, wherein said first terminal is supplied with said operation designation signals by said external device.

75. A one chip semiconductor integrated circuit device according to claim 73, wherein said predetermined logic level is one of logic "0" and "1".

76. A one chip semiconductor integrated circuit device according to claim 73, wherein said external device is a microprocessor.