Precharge-enable self boosting word line driver for an embedded DRAM

• US 5,923,596 A
• Filed: 05/08/1998
• Issued: 07/13/1999
• Est. Priority Date: 12/24/1996
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Chen, Lidong, Gillingham, Peter B., Wu, John
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/074,413
• Time in Patent Office: 431 Days
• Field of Search: 365/226, 365/230.06, 365/189.09, 365/189.11, 365/204, 365/193, 327/534, 327/536, 327/537
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A method of driving a DRAM word line comprising initiating a word line active cycle from a leading edge of a row enable signal, applying a first voltage to a word line following and as a result of said leading edge, receiving a trailing edge of the enable signal and applying a boosted voltage to the word line following and as a result of the trailing edge.

Claims

1. A voltage boost circuit comprising a p-channel FET capacitor having a gate forming a top plate and source and drain forming a bottom plate, an output node for providing a boosted output voltage connected to the top plate, a first p-channel FET having its source connected to a voltage source VDD and its drain connected to the top plate, a second p-channel FET having its drain connected to the top plate and a third p-channel FET having its drain connected to a gate of the second FET and its gate connected to ground (Vss), an inverter having its output connected to the bottom plate of the capacitor and its input to the source of the third FET, means for applying a first logic level of an RB signal derived from presence of a first logic level of a row enable signal to a gate of the first FET to cause it to conduct and thus raise the output node to VDD and to charge the top plate to VDD, means for applying an opposite logic level of said RB signal derived from a second logic level of the row enable signal to the gate of the first FET and for applying a first delayed signal DR derived from appearance of the second logic level of the row enable signal to the source of the second FET and to cause the second FET to pass onto said top plate and output node the voltage V_ss, means for applying a third signal CSD- derived from appearance of the second logic level of said row enable signal to the source of the third FET to cause it to conduct thus causing the second FET to cease conduction, means for applying said CSD- signal through the inverter to the bottom plate of the capacitor whereby the voltage at the top plate of the capacitor is lowered below V_ss to a negatively boosted voltage -V_boost.

2. A circuit as defined in claim 1 in which the high logic level of the CSD signal is derived from a second delayed signal being at low logic level and the row enable signal being at low logic level, thus defining a period during which -V_boost is applied to the wordline.

3. A circuit as defined in claim 1 in which the first logic level of the RB signal is logic high, the first logic level of the row enable signal is logic low, the second logic level of RB is logic low and the second logic level of the row enable signal is logic high.

4. A circuit as defined in claim 3 including means for bringing the RB signal back to the first logic level as a result of and following a delay from the falling edge of the row enable signal and for applying the RB signal to the gate of the first FET to cause it to conduct and thus raise the output node to VDD, thereby ending an interval during which the output node is negatively boosted to -V_boost.

5. A circuit as defined in claim 4 including means for terminating an interval of said DR signal and an interval of said CSD- signal, each said interval delayed from said falling edge of the row enable signal.

6. A circuit as defined in claim 5 in which said second edge of the row enable signal and a trailing edge of the DR signal are substantially simultaneous.

7. A circuit as defined in claim 6 including addressable means for coupling the -V_boost signal to at least one word line.

8. A circuit as defined in claim 7 including means for maintaining a plurality of unaddressed word lines at a voltage VDD.

9. A circuit as defined in claim 5 including programmable delay circuits for receiving said row enable signal and for providing said delayed RB, DR and CSD- signals.

10. A circuit as defined in claim 9 in which said programmable delay circuits are comprised of series circuits of inverters having programmable conductive switch bypass circuits.

11. A circuit as defined in claim 1 in which -V_boost is applied to the wordline via a wordline driver.

12. A circuit as defined in claim 1 whereby a beginning of the period during which -V_boost is applied to the wordlines is defined by the high logic level of the CSD- signal which in turn is derived from the combined presence of the row enable signal and a second delayed signal PHI- both being at low logic level, and whereby the end of said period is defined by the transition of both the RB and PHI- signals from low logic level to high logic level, both said transitions occurring as a result of a falling edge delay derived from the falling edge of the row enable signal.

13. A voltage boost circuit as defined in claim 1 in which the means for applying said CSD- signal to the bottom plate of the capacitor includes means for controlling the timing and interval of said voltage -V_boost by a second logic level of the row enable signal and a second delayed signal PHI- which is later than the first delayed signal DR.

14. A voltage boost circuit as defined in claim 13 including means for deriving a PHI- signal from said DR signal.