Precharge-enable self boosting word line driver for an embedded DRAM
First Claim
1. A voltage boost circuit comprising a p-channel FET capacitor having a gate forming a top plate and source and drain forming a bottom plate, an output node for providing a boosted output voltage connected to the top plate, a first p-channel FET having its source connected to a voltage source VDD and its drain connected to the top plate, a second p-channel FET having its drain connected to the top plate and a third p-channel FET having its drain connected to a gate of the second FET and its gate connected to ground (Vss), an inverter having its output connected to the bottom plate of the capacitor and its input to the source of the third FET, means for applying a first logic level of an RB signal derived from presence of a first logic level of a row enable signal to a gate of the first FET to cause it to conduct and thus raise the output node to VDD and to charge the top plate to VDD, means for applying an opposite logic level of said RB signal derived from a second logic level of the row enable signal to the gate of the first FET and for applying a first delayed signal DR derived from appearance of the second logic level of the row enable signal to the source of the second FET and to cause the second FET to pass onto said top plate and output node the voltage Vss, means for applying a third signal CSD- derived from appearance of the second logic level of said row enable signal to the source of the third FET to cause it to conduct thus causing the second FET to cease conduction, means for applying said CSD- signal through the inverter to the bottom plate of the capacitor whereby the voltage at the top plate of the capacitor is lowered below Vss to a negatively boosted voltage -Vboost.
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Abstract
A method of driving a DRAM word line comprising initiating a word line active cycle from a leading edge of a row enable signal, applying a first voltage to a word line following and as a result of said leading edge, receiving a trailing edge of the enable signal and applying a boosted voltage to the word line following and as a result of the trailing edge.
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Citations
14 Claims
- 1. A voltage boost circuit comprising a p-channel FET capacitor having a gate forming a top plate and source and drain forming a bottom plate, an output node for providing a boosted output voltage connected to the top plate, a first p-channel FET having its source connected to a voltage source VDD and its drain connected to the top plate, a second p-channel FET having its drain connected to the top plate and a third p-channel FET having its drain connected to a gate of the second FET and its gate connected to ground (Vss), an inverter having its output connected to the bottom plate of the capacitor and its input to the source of the third FET, means for applying a first logic level of an RB signal derived from presence of a first logic level of a row enable signal to a gate of the first FET to cause it to conduct and thus raise the output node to VDD and to charge the top plate to VDD, means for applying an opposite logic level of said RB signal derived from a second logic level of the row enable signal to the gate of the first FET and for applying a first delayed signal DR derived from appearance of the second logic level of the row enable signal to the source of the second FET and to cause the second FET to pass onto said top plate and output node the voltage Vss, means for applying a third signal CSD- derived from appearance of the second logic level of said row enable signal to the source of the third FET to cause it to conduct thus causing the second FET to cease conduction, means for applying said CSD- signal through the inverter to the bottom plate of the capacitor whereby the voltage at the top plate of the capacitor is lowered below Vss to a negatively boosted voltage -Vboost.
Specification