SONET/SDH receiver processor

• US 5,923,653 A
• Filed: 12/20/1995
• Issued: 07/13/1999
• Est. Priority Date: 04/21/1995
• Status: Expired due to Fees

• Current Assignee: VideoTele.com, Inc.
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Denton, I. Claude
• Primary Examiner(s): Jung, Min
• Application Number:
  US08/580,786
• Time in Patent Office: 1,301 Days
• Field of Search: 370/375, 370/376, 370/539, 370/541, 370/542, 370/536, 370/474, 370/476, 370/907, 370/535, 370/428, 359/135
• US Class Current: 370/375
• CPC Class Codes: H04J 2203/0005 Switching elements
• CPC Class Codes: H04J 2203/0025 Peripheral units
• CPC Class Codes: H04J 3/1611 Synchronous digital hierarchy [SDH] or SONET H04J3/1664 takes precedence for interactions with OTN
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A receiver processor for use in a SONET OC-48 or SDH test or network environment. The processor includes a 16:32 demultiplexer, descrambler, and a cross-connect enabling individual STS-3s in the incoming signal to be routed to selected STS-3s in the outgoing signal. An overhead and data capture function enables overhead and data bytes to be captured from each frame.

Claims

1. A SONET/SDH receiver processor for receiving an input SONET/SDH OC-48 signal, comprising:

(a) a 16;

32 demultiplexer receiving the input SONET/SDH signal;

(b) a descrambler connected to an output of said 16;

32 demultiplexer; and

(b) cross-connect means, connected to an output of said descrambler, for rearranging selected STS-12 signal components contained within the input SONET/SDH signal.

2. The SONET/SDH receiver processor as recited in claim 1 wherein the cross-connect means comprises:

a matrix of storage/switching elements for receiving the input SONET/SDH signal; and

control circuitry for synchronizing the storage/switching elements to the frame structure of the SONET/SDH signal.

3. The SONET/SDH receiver processor as recited in claim 2 wherein the storage/switching elements of the storage/switching matrix are arranged in rows respectively coupled to an output bus and columns with each storage/switching element having a bank number for determining whether the storage/switching element belongs to the column for driving the output bus.

4. The SONET/SDH receiver processor as recited in claim 2 wherein each storage/switching elements comprises:

at least two blocks of data storage connected in common for reading and writing selected bytes of the SONET/SDH signal in response to read and write enable signals and a clock signal;

at least two address latches coupled to the control circuitry for respectively holding a current address defining a current cross-connect pattern and an update address defining a new cross-connect pattern;

a multiplexer responsive to a first portion of the current address for selecting a selected byte of the SONET/SDH signal; and

control logic coupled to the blocks of data storage for generating the read and write enable signals in response to a word count being respectively compared to the bank number and the word count being compared to a second portion of the current address with a block select signal determining which block of data storage is written into and read from at any point in time.

5. The SONET/SDH receiver processor as recited in claim 1 wherein the descrambler further comprises:

a state vector register for receiving a state vector; and

a next state generator coupled to receive the state vector at an input for generating a new state vector by performing an exclusive-or function on the input state vector using a parallel implemented transformation matrix and coupling the new state vector to the state vector register.

6. The SONET/SDH receiver processor as recited in claim 5 wherein the descrambler further comprises timing circuitry for synchronously setting the state vector to the frame structure of the SONET/SDH signal and initiating loading of the state vector into the state vector register on each cycle of a clock input.

7. The SONET/SDH receiver processor as recited in claim 5 wherein the state vector register comprises a plurality of flip-flops having a plurality of bits.

8. The SONET/SDH receiver processor as recited in claim 7 wherein the state vector register comprises a plurality of flip-flops equalling thirty-two bits.

9. A SONET/SDH receiver processor for receiving an input SONET/SDH OC-48 signal comprising:

a descrambler having a state vector register for receiving a state vector and a next state generator coupled to receive the state vector at an input for generating a new state vector by performing an exclusive-or function on the input state vector using a parallel implemented transformation matrix and coupling the new state vector to the state vector register; and

a cross connect having a matrix of storage/switching elements for receiving the input SONET/SDH signal and control circuitry for synchronizing the storage/switching elements to the frame structure of the SONET/SDH signal, each storage/switching element having at least two blocks of data storage connected in common for reading and writing selected bytes of the SONET/SDH signal in response to read and write enable signals and a clock signal, at least two address latches coupled to the control circuitry for respectively holding a current address defining a current cross-connect pattern and an update address defining a new cross-connect pattern, a multiplexer responsive to a first portion of the current address for selecting a selected byte of the SONET/SDH signal, and control logic coupled to the blocks of data storage for generating the read and write enable signals in response to a word count being respectively compared to the bank number and the word count being compared to a second portion of the current address with a block select signal determining which block of data storage is written into and read from at any point in time.

10. The SONET/SDH receiver processor as recited in claim 9 wherein the descrambler further comprises timing circuitry for synchronously setting the state vector to the frame structure of the SONET/SDH signal and initiating loading of the state vector into the state vector register on each cycle of a clock input.

11. The SONET/SDH receiver processor as recited in claim 9 wherein the state vector register comprises a plurality of flip-flops having a plurality of bits.

12. The SONET/SDH receiver processor as recited in claim 11 wherein the state vector register comprises a plurality of flip-flops equalling thirty-two bits.

13. The SONET/SDH receiver processor as recited in claim 9 wherein the storage/switching elements of the storage/switching matrix are arranged in rows respectively coupled to an output bus and columns with each storage/switching element having a bank number for determining whether the storage/switching element belongs to the column for driving the output bus.

14. A cross-connect for use in a SONET/SDH receiver processor receiving an input SONET/SDH signal comprising:

a matrix of storage/switching elements for receiving the input SONET/SDH signal; and

control circuitry for synchronizing the storage/switching elements to the frame structure of the SONET/SDH signal, each storage/switching element having at least two blocks of data storage connected in common for reading and writing selected bytes of the SONET/SDH signal in response to read and write enable signals and a clock signal, at least two latches coupled to the control circuitry for respectively holding a current address defining a current cross-connect pattern and an update address defining a new cross-connect pattern, a multiplexer responsive to a first portion of the current address for selecting a selected byte of the SONET/SDH signal, and control logic coupled to the blocks of data storage for generating the read and write enable signals in response to a word count being respectively compared to the bank number and the word count being compared to a second portion of the current address with a block select signal determining which block of data storage is written into and read from at any point in time.

15. The cross-connect as recited in claim 14 wherein the storage/switching elements of the storage/switching matrix are arranged in rows respectively coupled to an output bus and columns with each storage/switching element having a bank number for determining whether the storage/switching element belongs to the column for driving the output bus.