Memory controller for decoding a compressed/encoded video data frame

• US 5,923,665 A
• Filed: 09/19/1997
• Issued: 07/13/1999
• Est. Priority Date: 09/30/1994
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Chan, Tzoyao, Hang, Chia-Lun, Sun, Yuanyuan, Sung, Chih-Ta, Soong, Jih-Hsien, Chang, Richard
• Primary Examiner(s): VU, HUY DUY
• Application Number:
  US08/934,027
• Time in Patent Office: 662 Days
• Field of Search: 370/677, 370/464, 370/522, 370/498, 370/354, 370/356, 370/265, 370/412, 370/476, 370/470, 370/471, 348/409, 348/410, 348/411, 348/412, 348/413, 348/414, 348/415, 348/416, 348/417, 348/418, 382/236, 382/239
• US Class Current: 370/477
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G11B 20/00007 Time or data compression or expansion audio compression based on psychoacoustics G10L19/00; data processing for reproducing audio data at different playback speeds G10L21/04; video compression H04N19/00; data compression per se H03M7/30
• CPC Class Codes: G11B 20/10527 Audio or video recording; Data buffering arrangements G11B20/12 - G11B20/18 take precedence
• CPC Class Codes: G11B 2220/213 Read-only discs
• CPC Class Codes: G11B 2220/2545 CDs
• CPC Class Codes: G11B 27/10 Indexing; Addressing; Timing or synchronising; Measuring tape travel
• CPC Class Codes: G11B 27/105 of operating discs
• CPC Class Codes: G11B 27/3027 used signal is digitally coded
• CPC Class Codes: G11B 27/3036 Time code signal
• CPC Class Codes: H04N 19/132 Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/427 Display on the fly, e.g. simultaneous writing to and reading from decoding memory
• CPC Class Codes: H04N 19/587 involving temporal sub-sampling or interpolation, e.g. decimation or subsequent interpolation of pictures in a video sequence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/4143 embedded in a Personal Computer [PC]
• CPC Class Codes: H04N 21/4341 Demultiplexing of audio and video streams
• CPC Class Codes: H04N 21/4435 Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02
• CPC Class Codes: H04N 5/775 between a recording apparatus and a television receiver
• CPC Class Codes: H04N 5/85 : on discs or drums
• CPC Class Codes: H04N 9/8042 : involving data reduction
• CPC Class Codes: H04N 9/8063 : using time division multiplex of the PCM audio and PCM video signals
• CPC Class Codes: H04N 9/8216 : using time division multiplex
• CPC Class Codes: H04N 9/87 : Regeneration of colour television signals H04N9/80 takes precedence

Abstract

A multimedia system includes an audio/video decompresser/decoder for decompressing/decoding a compressed/encoded audio/video data stream in order to generate video images for display on a display device and to generate audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder that has a novel memory controller and a novel method for displaying complete decoded/decompressed video frames on a display device without tearing. By use of selective storage of decoded/decompressed video frames in memory, tearing is prevented but information for predicting motion of a video segment is preserved.

Claims

1. A multimedia system having an audio/video decoding/decompressing circuit for decoding an encoded/compressed data stream comprising frames of encoded/compressed audio/video data, the circuit comprising:

a parser for separating the encoded/compressed data stream into encoded/compressed audio data and frames of encoded/compressed video data;

a memory having addressable storage, coupled to the parser, wherein the memory is address partitioned into a first region for temporary storage of the encoded/compressed audio data and the encoded/compressed video data and a second region comprising a plurality of slots for selectively storing frames of decoded/decompressed video data; and

a decoder, coupled to the memory, for receiving encoded/compressed video data from the first region of the memory, generating decoded/decompressed video data from the encoded/compressed video data, selectively storing frames of decoded/decompressed video data into corresponding ones of the plurality of slots in the memory, retrieving stored decoded/decompressed video data from the plurality of slots of the memory, and outputting decoded/decompressed video data as a video data stream.

2. The audio/video decoding circuit of claim 1, wherein the second region of the memory comprises three slots for storing decoded/decompressed video frames.

3. The audio/video decoding circuit of claim 1, wherein the second region of the memory comprises four slots for storing decoded/decompressed video frames.

4. The audio/video decoding circuit of claim 2, further comprising:

a graphics controller, coupled to the decoder and a video monitor, said graphics controller generating graphics data from the video data and displaying the graphics data as an image on the video monitor.

5. The audio/video decoding circuit of claim 3, further comprising:

a graphics controller, coupled to the decoder and a video monitor, said graphics controller generating graphics data from the video data and displaying the graphics data as an image on the video monitor.

6. The audio/video decoding circuit of claim 2, further comprising:

a graphics controller, coupled to the decoder and a digital display, said graphics controller generating graphics data from the video data and displaying the graphics data as an image on the digital display.

7. The audio/video decoding circuit of claim 3, further comprising:

a graphics controller, coupled to the decoder and a digital display, said graphics controller generating graphics data from the video data and displaying the graphics data as an image on the digital display.

8. The audio/video decoding circuit of claim 2, further comprising:

a television signal encoder, coupled to the decoder and a television display, said television signal encoder generating a television signal from the video data and displaying the television signal as an image on the television display.

9. The audio/video decoding circuit of claim 3, further comprising:

a television signal encoder, coupled to the decoder and a television display, said television signal encoder generating a television signal from the video data and displaying the television signal as an image on the television display.