Transmit clock generation system and method

• US 5,923,704 A
• Filed: 11/04/1996
• Issued: 07/13/1999
• Est. Priority Date: 03/25/1996
• Status: Expired due to Fees

• Current Assignee: Legerity Incorporated (Microsemi Semiconductor Corp.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Schnizlein, Paul
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Ghayour, Mohammad
• Application Number:
  US08/740,836
• Time in Patent Office: 981 Days
• Field of Search: 375/219, 375/222, 375/358, 375/362, 375/371, 375/373, 375/376, 331/74, 331/75
• US Class Current: 375/219
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A method for generating transmit clock timing of a first communications unit of a communications system. The communications system includes the first communications unit and a second communications unit, each capable of communications with the other. The first communications unit has a first internal clock and the second communications unit has a second internal clock. According to one example embodiment, the method includes the steps of receiving a receive data signal by the first communications unit from the second communications unit, adjusting a receive reference clock to the receive data signal to generate an adjusted receive reference clock that tracks the receive data signal, accumulating the adjustments made in the adjusting step, applying the adjustments accumulated to vary the first internal clock in order to slave the first internal clock to the second internal clock of the second communications unit so as to generate an adjusted receive reference clock that is the adjusted and slaved first internal clock, and deriving a transmit clock from the adjusted receive reference clock.

Claims

1. A method for generating transmit clock timing signal of a first communications unit of a communications system, the communications system including the first communications unit and a second communications unit, each capable of communication with the other, the first communications unit having a first internal clock and the second communications unit having a second internal clock, the method comprising the steps of:

the first communications unit receiving from the second communications unit a receive data signal;

accumulating phase errors in a receive reference clock relative to the receive data signal;

adjusting the receive reference clock to track the receive data signal and, in response, generating an adjusted receive reference clock that tracks the receive data signal;

accumulating the adjustments made in the adjusting step;

applying the adjustments accumulated to vary the first internal clock and tracking the second internal clock to slave the first internal clock to the second internal clock of the second communications unit so as to generate an adjusted receive reference clock that is the adjusted and slaved first internal clock; and

using a frequency divider/multiplier circuit, generating a transmit clock timing signal from the adjusted receive reference clock;

wherein the divider/multiplier circuit further comprising;

a first divider circuit having an input connected to an internal clock of the system;

an input of a multiply-by-n (n>

1) circuit connected to a first output of the first divider circuit;

a second divider circuit connected to an output of the multiply-by-n circuit; and

a third divider circuit connected to a second output of the first divider circuit, wherein the second divider circuit generates the transmit clock timing signal at an output of the second divider circuit.

2. The method of claim 1, wherein the adjusting step is performed by a phase lock loop.

3. The method of claim 2, wherein the accumulating step accumulates up and down signals from the phase lock loop.

4. The method of claim 1, wherein the applying step varies the first internal clock less frequently than the adjusting step varies the receive data signal.

5. The method of claim 4, wherein the transmit clock tracks the timing of the adjusted signal.

6. An apparatus for generating transmit clock timing of a first communications unit of a communications system, the communications system including the first communications unit and a second communications unit each capable of communications with the other, the first communications unit having a first internal clock and the second communications unit having a second internal clock, the second communications unit sending a receive data signal received by the first communications unit, the apparatus comprising:

an adjuster, incorporated with the first communications unit, for adjusting a receive reference clock to generate an adjusted receive reference clock that tracks the receive data signal;

an accumulator, communicably connected with the adjuster, for accumulating the adjustments made by the adjuster;

first means, communicably connected with the accumulator, for applying the adjustments accumulated to vary the first internal clock in order to slave the first internal clock to the second internal clock of the second communications unit so as to generate an adjusted signal that is the adjusted and slaved first internal clock; and

second means, including a frequency divider/multiplier circuit and communicably connected with the first means, for deriving a transmit clock from the adjusted signal;

wherein the divider/multiplier circuit further comprising;

a first divider circuit having an input connected to an internal clock of the system;

an input of a multiply-by-n (n>

1) circuit connected to a first output of the first divider circuit;

a second divider circuit connected to an output of the multiply-by-n circuit; and

a third divider circuit connected to a second output of the first divider circuit, wherein the second divider circuit generates the transmit clock timing signal at an output of the second divider circuit.

7. The apparatus of claim 6, wherein the adjuster includes a phase lock loop.

8. The apparatus of claim 7, wherein the accumulator is a counter having multiple states during each count repetition, the multiple states being each dictated by the adjuster.

9. The apparatus of claim 8, wherein the first means selectively applies the states of the counter in order to vary the first internal clock less frequently than the adjuster adjusts the receive reference clock to generate the adjusted signal.

10. The apparatus of claim 9, wherein the transmit clock derived by the second means has variation only as frequently as does the adjusted signal.

11. An apparatus for generating a transmit clock timing signal of a first communications unit of a communications system, the communications system including the first communications unit and a second communications unit each capable of communications with the other, the first communications unit having a first internal clock and the second communications unit having a second internal clock, the second communications unit sending a receive data signal received by the first communications unit, the apparatus including a divider chain circuit, the divider chain circuit comprising:

a first divider circuit having multiple states, responsive to a time-to-adjust signal, to generate an adjusted 1.024 MHz signal;

a multiply-by-three circuit, responsive to the multiple states of the first divider circuit, to take the logical OR of three of the multiple states, to generate an adjusted 3.072 MHz signal;

a second divider circuit, responsive to the adjusted 3.072 MHz signal, to generate a transmit clock, wherein the transmit clock is one-sixty-fourth of the rate of the adjusted 3.072 MHz signal; and

a third divider circuit, responsive to the adjusted 1.024 MHz signal, to generate the time-to-adjust signal,

wherein the second divider circuit generates the transmit clock timing signal.

12. An apparatus for generating a transmit clock timing signal of a first communications unit of a communications system, the communications system including the first communications unit and a second communications unit each capable of communications with the other, the first communications unit having a first internal clock and the second communications unit having a second internal clock, the second communications unit sending a receive data signal received by the first communications unit, the apparatus including a divider chain circuit, the divider chain circuit comprising:

a first divider circuit having an input connected to an internal clock of the system;

an input of a multiply-by-three circuit connected to a first output of the first divider circuit;

a second divider circuit connected to an output of the multiply-by-three circuit; and

a third divider circuit connected to a second output of the first divider circuit, wherein the second divider circuit generates the transmit clock timing signal at an output of the second divider circuit.

13. A method for generating transmit clock timing signal of a first communications unit of a communications system, the communications system including the first communications unit and a second communications unit, each capable of communication with the other, the first communications unit having a first internal clock and the second communications unit having a second internal clock, the method comprising the steps of:

the first communications unit receiving from the second communications unit a receive data signal;

accumulating phase errors in a receive reference clock relative to the receive data signal and adjusting the receive reference clock to track the receive data signal and, in response, generating an adjusted receive reference clock that tracks the receive data signal;

accumulating the adjustments made in the adjusting step;

applying the adjustments accumulated to vary the first internal clock and tracking the second internal clock to slave the first internal clock to the second internal clock of the second communications unit so as to generate an adjusted receive reference clock that is the adjusted and slaved first internal clock; and

generating a transmit clock timing signal from the adjusted receive reference clock;

wherein the divider/multiplier circuit further comprising;

a first divider circuit having an input connected to an internal clock of the system;

an input of a multiply-by-n (n>

1) circuit connected to a first output of the first divider circuit;

a second divider circuit connected to an output of the multiply-by-n circuit; and

a third divider circuit connected to a second output of the first divider circuit, wherein the second divider circuit generates the transmit clock timing signal at an output of the second divider circuit.

14. The method of claim 13, wherein the transmit clock tracks the timing of the adjusted signal.

15. A method for generating transmit clock timing signal of a first communications unit of a communications system, the communications system including the first communications unit and a second communications unit, each capable of communication with the other, the first communications unit having a first internal clock and the second communications unit having a second internal clock, the method comprising the steps of:

the first communications unit receiving from the second communications unit a receive data signal;

adjusting a receive reference clock to track the receive data signal and, in response, generating an adjusted receive reference clock that tracks the receive data signal;

modifying the first internal clock and tracking the second internal clock to slave the first internal clock to the second internal clock of the second communications unit so as to generate an adjusted receive reference clock that is the adjusted and slaved first internal clock, wherein the modifying step varies the first internal clock less frequently than the adjusting step varies the receive data signal; and

generating a transmit clock timing signal from the adjusted receive reference clock;

wherein the divider/multiplier circuit further comprising;

a first divider circuit having an input connected to an internal clock of the system;

an input of a multiply-by-n (n>

1) circuit connected to a first output of the first divider circuit;

a second divider circuit connected to an output of the multiply-by-n circuit; and

a third divider circuit connected to a second output of the first divider circuit, wherein the second divider circuit generates the transmit clock timing signal at an output of the second divider circuit.

16. The method of claim 15, wherein the transmit clock tracks the timing of the adjusted signal.

17. A method for generating transmit clock timing signal of a first communications unit of a communications system, the communications system including the first communications unit and a second communications unit, each capable of communication with the other, the first communications unit having a first internal clock and the second communications unit having a second internal clock, the method comprising the steps of:

the first communications unit receiving from the second communications unit a receive data signal;

adjusting a receive reference clock to track the receive data signal and, in response, generating an adjusted receive reference clock that tracks the receive data signal;

varying the first internal clock and tracking the second internal clock to slave the first internal clock to the second internal clock of the second communications unit so as to generate an adjusted receive reference clock that is the adjusted and slaved first internal clock; and

using a frequency divider/multiplier circuit, generating a transmit clock timing signal from the adjusted receive reference clock;

wherein the divider/multiplier circuit further comprising;

a first divider circuit having an input connected to an internal clock of the system;

an input of a multiply-by-n (n>

1) circuit connected to a first output of the first divider circuit;

a second divider circuit connected to an output of the multiply-by-n circuit; and

a third divider circuit connected to a second output of the first divider circuit, wherein the second divider circuit generates the transmit clock timing signal at an output of the second divider circuit.

18. The method of claim 17, wherein the transmit clock tracks the timing of the adjusted signal.

19. The method of claim 18, wherein the varying step varies the first internal clock less frequently than the adjusting step varies the receive data signal.

20. A transmit clock generation arrangement for generating transmit clock timing signal of a first communications unit of a communications system, the communications system including the first communications unit and a second communications unit, each capable of communication with the other, the transmit clock generation arrangement operating according to the method of claim 17.