Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus
First Claim
1. An arbitration circuit in a computer system having a first bus and a second bus, a plurality of first bus masters connected to the first bus, and a plurality of second bus masters connected to the second bus, the plurality of first bus masters providing a corresponding number of first bus request signals for the first bus, the plurality of second bus masters providing a corresponding number of second bus request signals for the second bus, the arbitration circuit comprising:
- a first arbiter for connection to the first bus, said first arbiter responsive to the plurality of first bus request signals for providing a first-to-second signal indicating a request from a first bus master for the second bus, said first arbiter including;
a first prioritizer responsive to the plurality of first bus request signals and a second-to-first request signal for determining the highest priority bus master on the first bus; and
a first granting circuit coupled to said first prioritizer for granting ownership of the first bus to the highest priority bus master; and
a second arbiter for connection to the second bus, said second arbiter responsive to the plurality of second bus request signals for providing the second-to-first request signal indicating a request from a second bus master for the first bus, said second arbiter including;
a first level arbiter responsive to the first-to-second request signal and the plurality of second bus request signals for performing a first level arbitration to determine priority between a plurality of requester types, said plurality of requestor types including a first requestor type comprising the first bus masters represented by said first-to-second request signal, the other plurality of requestor types each containing a different portion of the plurality of second bus masters;
a second level arbiter coupled to said first level arbiter for performing a second level arbitration if one of certain of said requestor types is determined to have the highest priority, said second level arbiter for determining which of the plurality of second bus masters in said highest priority requester type has the highest priority; and
a second granting circuit coupled to said first level arbiter and said second level arbiter for granting ownership of the second bus to the highest priority bus master.
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Accused Products
Abstract
Arbitration circuitry in a computer system having a plurality of arbiters for arbitrating requests from bus masters on a PCI bus and an EISA bus. Each of the PCI and EISA buses have a plurality of masters. The PCI bus utilizes a modified LRU arbitration scheme, while the EISA bus utilizes a rotating priority scheme. The arbiter on the EISA bus includes a first level of arbitration and a second level of arbitration. The first level is assigned a plurality of requester types to determine the priority between the requestor types. Certain of the first level requestor types include a plurality of devices. If one of those certain requestor types wins priority on the first level arbitration cycle, a second level arbitration is performed to determine the priority between the plurality of devices.
67 Citations
32 Claims
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1. An arbitration circuit in a computer system having a first bus and a second bus, a plurality of first bus masters connected to the first bus, and a plurality of second bus masters connected to the second bus, the plurality of first bus masters providing a corresponding number of first bus request signals for the first bus, the plurality of second bus masters providing a corresponding number of second bus request signals for the second bus, the arbitration circuit comprising:
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a first arbiter for connection to the first bus, said first arbiter responsive to the plurality of first bus request signals for providing a first-to-second signal indicating a request from a first bus master for the second bus, said first arbiter including; a first prioritizer responsive to the plurality of first bus request signals and a second-to-first request signal for determining the highest priority bus master on the first bus; and a first granting circuit coupled to said first prioritizer for granting ownership of the first bus to the highest priority bus master; and a second arbiter for connection to the second bus, said second arbiter responsive to the plurality of second bus request signals for providing the second-to-first request signal indicating a request from a second bus master for the first bus, said second arbiter including; a first level arbiter responsive to the first-to-second request signal and the plurality of second bus request signals for performing a first level arbitration to determine priority between a plurality of requester types, said plurality of requestor types including a first requestor type comprising the first bus masters represented by said first-to-second request signal, the other plurality of requestor types each containing a different portion of the plurality of second bus masters; a second level arbiter coupled to said first level arbiter for performing a second level arbitration if one of certain of said requestor types is determined to have the highest priority, said second level arbiter for determining which of the plurality of second bus masters in said highest priority requester type has the highest priority; and a second granting circuit coupled to said first level arbiter and said second level arbiter for granting ownership of the second bus to the highest priority bus master. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A computer system, comprising:
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a first bus; a second bus; a plurality of first bus masters connected to said first bus, wherein said plurality of first bus masters provide a corresponding number of first bus request signals for said first bus; a plurality of second bus masters connected to said second bus, wherein said plurality of second bus masters provide a corresponding number of second bus request signals for said second bus; a first arbiter coupled to said first bus, said first arbiter responsive to said plurality of first bus request signals for providing a first-to-second request signal indicating a request from a first bus master for said second bus, said first arbiter including; a first prioritizer responsive to said plurality of first bus request signals and a second-to-first request signal for determining the highest priority bus master on said first bus; and a first granting circuit coupled to said first prioritizer for granting ownership of said first bus to the highest priority bus master; and a second arbiter coupled to said second bus, said second arbiter responsive to said plurality of second bus request signals for providing the second-to-first request signal indicating a request from a second bus master for said first bus, said second arbiter including; a first level arbiter responsive to said first-to-second request signal and said plurality of second bus request signals for performing a first level arbitration to determine priority between a plurality of requestor types, said plurality of requester types including a first requester type comprising said first bus masters represented by said first-to-second request signal, said other plurality of requester types each containing a different portion of said plurality of second bus masters; a second level arbiter coupled to said first level arbiter for performing a second level arbitration if one of certain of said requestor types is determined to have the highest priority, said second level arbiter for determining which of said plurality of second bus masters in said highest priority requestor type has the highest priority; and a second granting circuit coupled to said first level arbiter and said second level arbiter for granting ownership of said second bus to the highest priority bus master. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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Specification