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Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus

  • US 5,923,859 A
  • Filed: 11/19/1997
  • Issued: 07/13/1999
  • Est. Priority Date: 04/13/1995
  • Status: Expired due to Term
First Claim
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1. An arbitration circuit in a computer system having a first bus and a second bus, a plurality of first bus masters connected to the first bus, and a plurality of second bus masters connected to the second bus, the plurality of first bus masters providing a corresponding number of first bus request signals for the first bus, the plurality of second bus masters providing a corresponding number of second bus request signals for the second bus, the arbitration circuit comprising:

  • a first arbiter for connection to the first bus, said first arbiter responsive to the plurality of first bus request signals for providing a first-to-second signal indicating a request from a first bus master for the second bus, said first arbiter including;

    a first prioritizer responsive to the plurality of first bus request signals and a second-to-first request signal for determining the highest priority bus master on the first bus; and

    a first granting circuit coupled to said first prioritizer for granting ownership of the first bus to the highest priority bus master; and

    a second arbiter for connection to the second bus, said second arbiter responsive to the plurality of second bus request signals for providing the second-to-first request signal indicating a request from a second bus master for the first bus, said second arbiter including;

    a first level arbiter responsive to the first-to-second request signal and the plurality of second bus request signals for performing a first level arbitration to determine priority between a plurality of requester types, said plurality of requestor types including a first requestor type comprising the first bus masters represented by said first-to-second request signal, the other plurality of requestor types each containing a different portion of the plurality of second bus masters;

    a second level arbiter coupled to said first level arbiter for performing a second level arbitration if one of certain of said requestor types is determined to have the highest priority, said second level arbiter for determining which of the plurality of second bus masters in said highest priority requester type has the highest priority; and

    a second granting circuit coupled to said first level arbiter and said second level arbiter for granting ownership of the second bus to the highest priority bus master.

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