Apparatus, method and system for remote peripheral component interconnect bus using accelerated graphics port logic circuits

• US 5,923,860 A
• Filed: 06/25/1997
• Issued: 07/13/1999
• Est. Priority Date: 06/25/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Olarig, Sompong P.
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/882,090
• Time in Patent Office: 748 Days
• Field of Search: 395/306, 395/308, 395/309, 395/284, 395/828
• US Class Current: 710/306
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a remote peripheral component interconnect ("remote-PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and the remote-PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or a remote-PCI bus bridge is to be implemented. Selection of the type of bus bridge (AGP or remote-PCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a remote-PCI device connected to the common AGP/remote-PCI bus.

Claims

1. A computer system having a core logic chip set configurable for either an accelerated graphics port (AGP) bus or a remote peripheral component interconnect (PCI) bus, said system comprising:

a central processing unit connected to a host bus;

a random access memory connected to a random access memory bus;

a core logic chip set connected to the host bus and the random access memory bus;

said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and an accelerated graphics port bus, and a third interface bridge between the random access memory bus and the accelerated graphics port bus;

said core logic chip set configured as a fourth interface bridge between the host bus and a remote peripheral component interconnect bus; and

said core logic chip set configured as a fifth interface bridge between the random access memory bus and the remote component interconnect bus.

2. The computer system of claim 1, said computer system further comprising at least one additional central processing unit connected to said host bus.

3. The computer system of claim 1, wherein the core logic chip set is at least one integrated circuit.

4. The computer system of claim 3, wherein the at least one integrated circuit core logic chip set is at least one application specific integrated circuit.

5. The computer system of claim 3, wherein the at least one integrated circuit core logic chip set is at least one programmable logic array integrated circuit.

6. The computer system of claim 1, further comprising at least one peripheral component interconnect device, the at least one peripheral component interconnect device connected to the remote peripheral component interconnect bus.

7. The computer system of claim 1, wherein said fourth and fifth interface bridges include a cable interface comprising drivers and receivers for interfacing with a plurality of insulated wires in an expansion cable.

8. The computer system of claim 7, wherein the drivers are differential drivers and the receivers are differential receivers.

9. The computer system of claim 8, wherein the plurality of insulated wires in the expansion cable are arranged into a plurality of twisted pairs.

10. The computer system of claim 1, wherein the host bus, random access memory bus, and accelerated graphics port bus are on a first printed circuit board.

11. The computer system of claim 10, wherein the remote peripheral component interconnect bus is on a second printed circuit board.

12. The computer system of claim 11, wherein a second cable interface is on said second printed circuit board and connected to the remote peripheral component interconnect bus.

13. The computer system of claim 1, wherein the fourth and fifth interface bridges of said core logic chip set are configured for the remote peripheral component interconnect bus by an electrical signal sent from a hardwired jumper circuit located on the first printed circuit board.

14. The computer system of claim 1, wherein the fourth and fifth interface bridges of said core logic chip set are configured for the remote peripheral component interconnect bus by software control of said core logic chip set.

15. The computer system of claim 14, wherein the fourth and fifth interface bridges of said core logic chip set are configured for the remote peripheral component interconnect bus when a peripheral component interconnect device is detected on the remote peripheral component interconnect bus.

16. The computer system of claim 15, wherein configuration of said core logic chip set is done during power on self test of the computer system.

17. The computer system of claim 15, wherein configuration of said core logic chip set is done during configuration of the computer system.

18. A computer system having a core logic chip set configurable for either an accelerated graphics port (AGP) bus or a remote peripheral component interconnect (PCI) bus, said system comprising:

a central processing unit connected to a host bus;

a random access memory connected to a random access memory bus;

a core logic chip set connected to the host bus and the random access memory bus;

said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus;

said core logic chip set configured as a fourth interface bridge between the host bus and a remote peripheral component interconnect bus; and

said core logic chip set configured as a fifth interface bridge between the random access memory bus and the remote component interconnect bus;

wherein said fourth and fifth interface bridges include a cable interface comprising drivers and receivers for interfacing with a plurality of insulated wires in an expansion cable.

19. The computer system of claim 18, wherein the drivers are differential drivers and the receivers are differential receivers.

20. The computer system of claim 19, wherein the plurality of insulated wires in the expansion cable are arranged into a plurality of twisted pairs.

21. A computer system having a core logic chip set configurable for either an accelerated graphics port (AGP) bus or a remote peripheral component interconnect (PCI) bus said system comprising:

a central processing unit connected to a host bus;

a random access memory connected to a random access memory bus;

a core logic chip set connected to the host bus and the random access memory bus;

said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus;

said core logic chip set configured as a fourth interface bridge between the host bus and a remote peripheral component interconnect bus; and

said core logic chip set configured as a fifth interface bridge between the random access memory bus and the remote component interconnect bus;

wherein the host bus, random access memory bus and first peripheral component interconnect bus are on a first printed circuit board.

22. The computer system of claim 21, wherein the remote peripheral component interconnect bus is on a second printed circuit board.

23. The computer system of claim 22, wherein a second cable interface is on said second printed circuit board and connected to the remote peripheral component interconnect bus.

24. A computer system having a core logic chip set configurable for either an accelerated graphics port (AGP) bus or a remote peripheral component interconnect (PCI) bus, said system comprising:

a central processing unit connected to a host bus;

a random access memory connected to a random access memory bus;

a core logic chip set connected to the host bus and the random access memory bus;

said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus;

said core logic chip set configured as a fourth interface bridge between the host bus and a remote peripheral component interconnect bus; and

said core logic chip set configured as a fifth interface bridge between the random access memory bus and the remote component interconnect bus;

wherein the fourth and fifth interface bridges of said core logic chip set are configured for the remote peripheral component interconnect bus by an electrical signal sent from a hardwired jumper circuit located on the first printed circuit board.

25. A computer system having a core logic chip set configurable for either an accelerated graphics port (AGP) bus or a remote peripheral component interconnect (PCI) bus, said system comprising:

a central processing unit connected to a host bus;

a random access memory connected to a random access memory bus;

a core logic chip set connected to the host bus and the random access memory bus;

said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus;

said core logic chip set configured as a fourth interface bridge between the host bus and a remote peripheral component interconnect bus; and

said core logic chip set configured as a fifth interface bridge between the random access memory bus and the remote component interconnect bus;

wherein the fourth and fifth interface bridges of said core logic chip set are configured for the remote peripheral component interconnect bus by software control of said core logic chip set.

26. The computer system of claim 25, wherein the fourth and fifth interface bridges of said core logic chip set are configured for the remote peripheral component interconnect bus when a peripheral component interconnect device is detected on the remote peripheral component interconnect bus.

27. The computer system of claim 26, wherein configuration of said core logic chip set is done during power on self test of the computer system.

28. The computer system of claim 26, wherein configuration of said core logic chip set is done during configuration of the computer system.

29. A method, in a computer system, of configuring a core logic chip set for either an accelerated graphics port (AGP) bus or a remote peripheral component interconnect (PCI) bus, said method comprising the steps of:

providing a central processing unit connected to a host bus;

providing a random access memory connected to a random access memory bus;

providing a core logic chip set connected to the host bus and the random access memory bus;

configuring said core logic chip set as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus; and

configuring said core logic chip set as a fourth interface bridge between the host bus and a remote peripheral component interconnect bus and a fifth interface bridge between the random access memory bus and the remote peripheral component interconnect bus when a configuration signal is applied to said core logic chip set.

30. The method of claim 29, wherein the configuration signal is applied to said core logic chip set when a peripheral component interconnect device is detected on the remote peripheral component interconnect bus.

31. The method of claim 30, wherein the peripheral component interconnect device is detected during a power on self test of the computer system.

32. The method of claim 30, wherein the peripheral component interconnect device is detected during a configuration of the computer system.

33. A core logic chip set configurable for either an accelerated graphics port (AGP) bus or a remote peripheral component interconnect (PCI) bus, comprising:

an accelerated graphics port (AGP) request queue;

an AGP reply queue;

an AGP data and control logic;

an AGP and PCI arbiter;

a PCI data and control logic;

a PCI to PCI bridge; and

an expansion cable interface adapted for connection to an expansion cable;

said AGP request and reply queues connected to a memory interface and control logic, said memory and interface control logic adapted for connection to a computer system random access memory;

said AGP data and control logic connected to said memory and interface control logic;

said PCI data and control logic connected to said memory and interface control logic;

said AGP data and control logic and PCI data and control logic connected to a host bus interface, said host bus interface adapted for connection to a computer system host bus having at least one central processing connected thereto;

a host to PCI bus bridge connected to said host bus interface and adapted for connection to a computer system primary PCI bus;

said PCI to PCI bridge connected to said AGP data and control logic, and said PCI data and control logic, wherein said PCI to PCI bridge transfers PCI information transactions between said Host to primary PCI bus bridge and said AGP data and control logic, and said PCI data and control logic;

said AGP data and control logic, said PCI data and control logic, and said AGP and PCI arbiter adapted for connection to either an AGP bus or a PCI bus; and

said expansion cable interface connected to said PCI data and control logic.

34. The core logic chip set according to claim 33, wherein said PCI data and control logic, and said AGP and PCI arbiter are adapted for connection to a plurality of PCI devices.

35. The core logic chip set according to claim 33, wherein said PCI data and control logic, and said AGP and PCI arbiter are configured for the plurality of PCI devices by a hardware jumper applying a control signal to said core logic chip set.

36. The core logic chip set according to claim 33, wherein said PCI data and control logic, and said AGP and PCI arbiter are configured for the plurality of PCI devices by software configuring a control register in said core logic chip set.