Host processor and coprocessor arrangement for processing platform-independent code
First Claim
1. A coprocessor arrangement for processing platform-independent program code, comprising:
- an expansion bus interface circuit;
an instruction cache coupled to the expansion bus interface circuit;
a platform-independent code processing unit coupled to the instruction cache;
an internal control register coupled to the expansion bus interface circuit and having an input port for providing external access thereto, the control register arranged to provide an operational state for the processing unit; and
a program counter register coupled to the expansion bus interface circuit and coupled to the platform-independent code processing unit, the program counter register arranged to store an address of a next platform-independent instruction to be processed.
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Accused Products
Abstract
A multiple processor circuit arrangement utilizes a host processor which controls the operational state of a coprocessor by programming internal control registers on the coprocessor. The host processor and coprocessor are coupled to an expansion bus, and the coprocessor is adapted to execute platform-independent code on behalf of the host processor. In addition, a stack-based processor utilizes a stack cache for accelerating stack access operations and thereby accelerating the overall performance of the processor. When the stack-based processor is utilized as the coprocessor in the aforementioned host/coprocessor computer system, the coprocessor is optimized to process platform-independent program code such as Java bytecodes, thereby permitting fast and efficient execution of both program code native to the master processor as well as platform-independent program code that is, effectively, native to the coprocessor.
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Citations
36 Claims
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1. A coprocessor arrangement for processing platform-independent program code, comprising:
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an expansion bus interface circuit; an instruction cache coupled to the expansion bus interface circuit; a platform-independent code processing unit coupled to the instruction cache; an internal control register coupled to the expansion bus interface circuit and having an input port for providing external access thereto, the control register arranged to provide an operational state for the processing unit; and a program counter register coupled to the expansion bus interface circuit and coupled to the platform-independent code processing unit, the program counter register arranged to store an address of a next platform-independent instruction to be processed. - View Dependent Claims (2, 3, 4)
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5. A coprocessor arrangement for process ing platform-independent program code, comprising:
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interface means for providing access to an expansion bus; instruction cache means coupled to the interface means for providing and controlling cache storage of platform-independent program code; processing means coupled to the instruction cache means for processing platform-independent code; an internal control register coupled to the interface means and having an input port for providing external access thereto, the control register for providing an operational state for the processing means; and a program counter register coupled to the interface means and coupled to the processing means for referencing an address of a next platform-independent instruction to be processed. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A computer system, comprising:
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a local bus; a host processor coupled to the local bus for managing execution of platform-independent code; a memory coupled to the local bus for storing the platform-independent code; an expansion bus bridge coupled to the local bus; an expansion bus coupled to the expansion bus bridge; and a coprocessor coupled to the expansion bus for processing the platform-independent code as directed by the host processor, the coprocessing including, an expansion bus interface circuit; an instruction cache coupled to the expansion bus interface circuit; a platform-independent code processing unit coupled to the instruction cache; an internal control register coupled to the expansion bus interface circuit and having an input port for providing external access thereto, the control register for providing an operational state for the coprocessor; and a program counter register coupled to the expansion bus interface circuit and coupled to the platform-independent code processing unit for referencing an address of a next platform-independent instruction to be executed. - View Dependent Claims (17, 18, 19)
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20. A computer system, comprising:
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a local bus; a host processor coupled to the local bus for managing execution of platform-independent code; a memory coupled to the local bus for storing the platform-independent code; an expansion bus bridge coupled to the local bus; an expansion bus coupled to the expansion bus bridge; and a coprocessor coupled to the expansion bus for processing the platform-independent code as directed by the host processor, the coprocessing including, interface circuit means for providing access to the expansion bus; instruction cache means coupled to the interface means for providing and controlling cache storage of the platform-independent program code; processing means coupled to the instruction cache for executing the platform-independent code; an internal control register coupled to the interface means and having an input port for providing external access thereto, the control register for providing an operational state for the coprocessor; and a program counter register coupled to the interface means and coupled to the control unit for referencing an address of a next platform-independent instruction to be executed by the processing means. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method for processing platform independent code, comprising the steps of:
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(a) receiving platform-independent code at a host processor; (b) storing the platform-independent code in a memory; (c) transmitting an activation signal addressed to a coprocessor from the host processor to an expansion bus bridge; (d) transmitting the activation signal from the bridge to the coprocessor via an expansion bus; (e) activating the coprocessor in response to the activation signal; and (f) processing the platform-independent code by the coprocessor. - View Dependent Claims (32, 33, 34, 35, 36)
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Specification