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Host processor and coprocessor arrangement for processing platform-independent code

  • US 5,923,892 A
  • Filed: 10/27/1997
  • Issued: 07/13/1999
  • Est. Priority Date: 10/27/1997
  • Status: Expired due to Term
First Claim
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1. A coprocessor arrangement for processing platform-independent program code, comprising:

  • an expansion bus interface circuit;

    an instruction cache coupled to the expansion bus interface circuit;

    a platform-independent code processing unit coupled to the instruction cache;

    an internal control register coupled to the expansion bus interface circuit and having an input port for providing external access thereto, the control register arranged to provide an operational state for the processing unit; and

    a program counter register coupled to the expansion bus interface circuit and coupled to the platform-independent code processing unit, the program counter register arranged to store an address of a next platform-independent instruction to be processed.

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