Nitride encapsulated thin film transistor fabrication technique

• US 5,923,964 A
• Filed: 01/14/1997
• Issued: 07/13/1999
• Est. Priority Date: 10/16/1995
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Li, Jia
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US08/783,111
• Time in Patent Office: 910 Days
• Field of Search: 438/158, 438/287
• US Class Current: 438/158
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A thin film transistor includes a thin film transistor body above a gate electrode. The thin film transistor body is hydrogenated to prevent the transistor body from apparently capturing and releasing electrons. The transistor body itself is coated with an upper and lower layer of silicon nitride to prevent the trapped hydrogen from migrating out of the transistor body over time. This is formed by depositing a layer of silicon dioxide, then a layer of silicon nitride over the gate electrode, followed by deposition of a polysilicon layer which is then etched to form the transistor body. This is hydrogenated after threshold adjustment implant and source/drain implant and subsequently coated with an upper sealing layer of silicon nitride. This enables the establishment of relatively high lon/loff ratio and improves the reliability of the transistor.

Claims

1. A method of forming a thin film transistor comprising depositing a first sealing layer over a gate electrode;

depositing a semiconductor layer;

etching said semiconductor layer to establish a transistor body above said gate electrode;

implanting ions of group III or group V elements to adjust a threshold voltage of the transistor and to form a source and a drain of the transistor;

hydrogenating said transistor body and coating said transistor body with a second sealing layer;

thereby forming a thin film transistor wherein said transistor body is a hydrogenated semiconductor transistor body adjacent said gate electrode separated from said gate electrode by a gate dielectric;

wherein said transistor body has a top surface covered by said second sealing layer and a bottom surface covered by said first sealing layer and separating said transistor body from said gate electrode;

wherein said first and second searing layers are effective to prevent hydrogen migration from said transistor body.

2. The method claimed in claim 1 wherein said sealing layer comprises silicon nitride.

3. The method claimed in claim 2 wherein said semiconductor comprises polysilicon.

4. The method claimed in claim 3 further comprising coating said gate electrode with silicon dioxide prior to depositing said first layer of silicon nitride.

5. The method claimed in claimed 4 comprising coating said polysilicon layer with silicon dioxide prior to etching said polysilicon transistor body layer.

6. A method of forming a thin film transistor comprising forming a gate electrode on a substrate

depositing a first layer of silicon dioxide over said gate electrodes;

depositing a first layer of silicon nitride over said first layer of silicon dioxide;

depositing a layer of polysilicon over said first layer of silicon nitride;

depositing a second layer of silicon dioxide over said polysilicon layer and etching said second layer of silicon dioxide, said polysilicon layer to establish a thin film transistor body;

implanting ions of group III or group V elements to adjust a threshold voltage of the transistor and to form a source and a drain for said transistor;

hydrogenating said transistor body to bind hydrogen to dangling bonds in grain boundaries of said transistor body;

depositing a second layer of silicon nitride over said transistor body;

wherein said first layer of silicon nitride and said second layer of silicon nitride are effective to prevent hydrogen migration from said transistor body.