Cascading transistor gate and method for fabricating the same

• US 5,923,981 A
• Filed: 12/31/1996
• Issued: 07/13/1999
• Est. Priority Date: 12/31/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Qian, Qi-De
• Primary Examiner(s): Brown, Peter Toby
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US08/777,600
• Time in Patent Office: 924 Days
• Field of Search: 438/176, 438/177, 438/183, 438/283, 438/284, 438/299, 438/578, 438/585, 438/945, 438/947, 438/197, 438/301
• US Class Current: 438/284
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing

Abstract

A cascading transistor gate structure and method for fabricating the same are disclosed. A substrate is provided, and a layer of gate dielectric material is formed over the substrate. A layer of electrically conductive material is formed over the gate dielectric. A layer of hard mask material is formed on the layer of electrically conductive material. A photoresist mask is used to pattern the layer of hard mask material to form a hard mask. A layer of spacer material is deposited over the existing structures, and the layer of spacer material is etched to form a pair of spacers adjacent to the hard mask. The hard mask is removed, leaving the spacers. The layer of electrically conductive material is etched in alignment with the spacers. The spacers are then removed, revealing two transistor gates. A conductive region in formed in the substrate between the two gates. The two gates operate in tandem, yielding a cascading gate with an effective length that is the lengths of the two gates combined.

Claims

1. A method of forming a cascading transistor gate, comprising the steps of:

forming a dielectric layer on a substrate;

forming a layer of electrically conductive material on the dielectric layer;

forming a mask on the layer of electrically conductive material, the mask having a first edge and a second edge;

forming a first spacer on said layer of electrically conductive material adjacent to the first edge;

forming a second spacer on said layer of electrically conductive material adjacent to the second edge;

removing the mask;

etching the electrically conductive material in alignment with the first and second spacers;

removing the first and second spacers in order to reveal a first gate and a second gate; and

forming an electrically conductive region in the substrate between the first gate and the second gate.

2. The method of forming a cascading transistor gate of claim 1, wherein the substrate comprises silicon, and further wherein the step of forming an electrically conductive region in the substrate comprises doping the silicon with boron.

3. The method of forming a cascading transistor gate of claim 1, wherein the substrate comprises silicon, and further wherein the step of forming an electrically conductive region in the substrate comprises doping the silicon with arsenic.

4. A method of forming a cascading transistor gate, comprising the steps of:

forming a dielectric layer on a substrate;

forming a layer of electrically conductive material on the dielectric layer;

forming a layer of mask material over the layer of electrically conductive material;

patterning the layer of mask material using photolithography, the mask having a first edge and a second edge;

forming a layer of spacer material over the mask and electrically conductive material;

etching the spacer material to form a first spacer adjacent to the first edge and a second spacer adjacent to the second edge;

removing the mask;

etching the electrically conductive material in alignment with the first and second spacers;

removing the first and second spacers in order to reveal a first gate and a second gate; and

forming a conductive region in the substrate between the first gate and the second gate.

5. The method of forming a cascading transistor gate of claim 4, wherein the mask material comprises silicon dioxide.

6. The method of forming a cascading transistor gate of claim 4, wherein the electrically conductive material comprises polysilicon.

7. The method of forming a cascading transistor gate of claim 4, wherein the step of forming a layer of spacer material further comprises the step of performing a conformal pattern transfer layer deposition of the spacer material.

8. The method of forming a cascading transistor gate of claim 7, wherein the step of etching the spacer material is accomplished by using a reactive ion etching process.

9. The method of forming a cascading transistor gate of claim 8, wherein the spacer material comprises silicon nitride.

10. The method of forming a cascading transistor gate of claim 4, wherein the substrate comprises silicon.

11. The method of forming a cascading transistor gate of claim 10, wherein the step of forming a conductive region further comprises the step of doping the conductive region with boron.

12. The method of forming a cascading transistor gate of claim 11, wherein the step of doping the conductive region with boron is accomplished by ion implantation.

13. The method of forming a cascading transistor gate of claim 10, wherein the step of forming a conductive region further comprises the step of doping the conductive region with arsenic.

14. The method of forming a cascading transistor gate of claim 13, wherein the step of doping the conductive region with arsenic is accomplished by ion implanation.