Difference capture timer

• US 5,925,136 A
• Filed: 03/02/1998
• Issued: 07/20/1999
• Est. Priority Date: 03/02/1998
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Watts, Charles E. Jr.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US09/032,901
• Time in Patent Office: 505 Days
• Field of Search: 713/500, 713/502
• US Class Current: 713/502
• CPC Class Codes: G04F 10/04 by counting pulses or half-cycles of an ac G04F10/005 takes precedence

Abstract

A difference capture circuit for determining the duration of a digital signal pulse. The difference circuit includes a branch couplable to a standard counter for activating the counter to count as a function of a system clock pulse, and a triggering circuit couplable to a standard capture register for fetching the count from the counter. The difference capture circuit may be incorporated into standard timer unit circuitry and is designed to calculate the difference between either the rise and fall times for an incoming signal, or the rise to rise time of that signal. Adding the difference capture circuit to a timing unit eliminates the need to use RAM, and minimizes processor resources, in obtaining the timing associated with a signal change.

Claims

1. A difference capture circuit for obtaining the duration of a digital signal pulse characterized by a first event and a second event, said difference capture circuit including an incoming signal node for receiving the digital signal pulse, said difference capture circuit comprising:

a. a counter-initiate circuit coupled between said incoming signal node and a counter, wherein the counter is coupled to a system clock; and

b. a triggering circuit coupled between said incoming signal node and a capture register,

wherein the first event activates said counter-initiate circuit such that the counter begins to count pulses associated with the system clock, wherein the second event activates said triggering circuit such that said capture register fetches a count from the counter upon the occurrence of the second event, and wherein the count fetched from the counter is directly related to the difference in time between the first event and the second event.

2. The difference capture circuit as claimed in claim 1 wherein the first event is a rising edge of the digital signal pulse and the second event is a falling edge of the digital signal pulse, said triggering circuit further comprising a falling-edge branch for triggering the capture register to fetch the count from the counter upon receiving the falling edge at said incoming signal node.

3. The difference capture circuit as claimed in claim 1 wherein the first event is a first rising edge of the digital signal pulse and the second event is a second rising edge of the digital signal pulse, said triggering circuit further comprising a rising-edge branch for triggering the capture register to fetch the count from the counter upon receiving the second rising edge at said incoming signal node.

4. The difference capture circuit as claimed in claim 1 wherein said counter-initiate circuit includes a counter-initiate flip-flop coupled to said incoming signal node, and a counter-initiate AND gate having a first input coupled to the system clock and a second input coupled to an output of said counter-initiate flip-flop, wherein an output of said counter-initiate AND gate is a triggering input to the counter.

5. The difference capture circuit as claimed in claim 4 wherein said triggering circuit includes:

a. a trigger flip-flop coupled to said incoming signal node;

b. a first trigger AND gate having a first input coupled to said output of said counter-initiate flip-flop, a second input coupled to said incoming signal node, and a third input coupled to a trigger input node; and

c. a second trigger AND gate having a first input coupled to an output of said trigger flip-flop, a second input coupled to said incoming signal node, and a third input coupled to said trigger input node.

6. The difference capture circuit as claimed in claim 5 wherein an output of said first trigger AND gate and an output of said second trigger AND gate are coupled to the capture register through an OR gate.

7. The difference capture circuit as claimed in claim 6 with said triggering circuit further comprising a first inverter coupling said incoming signal node to said first trigger AND gate and a second inverter coupling said trigger input node to said first trigger AND gate.

8. The difference capture circuit as claimed in claim 1 further comprising a reload circuit between said counter-initiate circuit and the counter, wherein said reload circuit sets the count of said counter to zero when there is no output from said counter-initiate circuit, and said reload circuit sets the counter for counting upward from zero when output from said counter-initiate circuit is logic HIGH.