Microcomputer capable of preventing writing errors in a non-volatile memory

• US 5,925,139 A
• Filed: 03/20/1997
• Issued: 07/20/1999
• Est. Priority Date: 03/25/1996
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamada, Susumu, Watanabe, Toru, Yamasaki, Shinichi
• Primary Examiner(s): Auve, Glenn A.
• Assistant Examiner(s): Jean, Frantz B.
• Application Number:
  US08/821,598
• Time in Patent Office: 852 Days
• Field of Search: 711/152, 711/155, 714/42, 714/54, 714/14
• US Class Current: 714/14
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges

Abstract

When data are to be written in an EEPROM (1), a CPU (2) sets a flag (12). A voltage booster (13) boosts the power voltage in compliance with the setting of the flag (12). A voltage boost detector (14) detects whether the output of the voltage booster (13) is in voltage boost state. If the output of the voltage booster (13) is not in voltage boost state, a latch (15) is reset and the EEPROM (1) is not permitted to switch to write mode. As a result, it is possible to prevent incorrect data writing in the EEPROM (1) even when the flag (12) has been incorrectly set.

Claims

1. A microcomputer containing a non-volatile memory capable of reading and writing data, comprising:

a CPU for executing program commands;

a flag which is set to a first logic value by the CPU based on a program command;

a voltage booster for boosting a power voltage and outputting a boosted voltage when the flag is set to the first logic value;

a detector for detecting the boosted voltage and outputting a second logic value when the detected voltage is lower than a predetermined level and a third logic value when the detected voltage is equal to or higher than the predetermined level;

a latch which is reset when the output of the detector is the second logic value and is released from being reset when the output of the detector is the third logic value; and

a memory controller for setting the non-volatile memory to a state wherein data can be written when the latch output is set to a logic value different from the logic value when the latch is reset.

2. A microcomputer according to claim 1, wherein:

data are written in the non-volatile memory using a power voltage boosted by the voltage booster.

3. A microcomputer containing a non-volatile memory storing a plurality of program commands and capable of reading and writing data, comprising:

a CPU for executing program commands, the CPU having an address counter for sending an address instruction to the non-volatile memory;

a flag which is set to a first logic value by the CPU based on a program command;

a detector for outputting a logic value based on a power voltage state when the flag is set at the first logic value;

a latch which is reset when the output of the detector is a second logic value and is released from being reset when the output of the detector is a third logic value; and

a memory controller for setting the non-volatile memory to a state to permit writing of data when the latch output is set to a logic value different from the logic value when the latch is reset,

wherein the CPU sets the address counter to a specific value based on the output of the detector when the flag is set to the first logic value, and

wherein the CPU determines whether or not the flag is set correctly by decoding a program command read out from the non-volatile memory when the address counter is set to the specific value.

4. A microcomputer according to claim 3, wherein

when the CPU has determined that the flag has been incorrectly set, the CPU inhibits the latch from reaching a logic value different from the reset value.

5. A microcomputer containing a non-volatile memory capable of reading and writing data, comprising:

a CPU for executing program commands;

a flag which is set to a first logic value by the CPU based on a program command;

a detector for outputting a logic value based on a power voltage state when the flag is set at the first logic value;

a latch which is reset when the output of the detector is a second logic value and is released from being reset when the output of the detector is a third logic value; and

a memory controller for setting the non-volatile memory to a state to permit writing of data when the latch output is set to a logic value different from the logic value when the latch is reset,

wherein when the memory controller permits writing of data in the non-volatile memory, the CPU ignores output read out from the non-volatile memory.

6. A microcomputer according to claim 5, wherein

the non-volatile memory is partitioned into first and second regions;

and

a program command for writing second region data is stored in the first region.

7. A microcomputer containing a non-volatile memory capable of reading and writing data, comprising:

a flag set to a specific logic value when data are rewritten in the non-volatile memory;

a voltage booster for boosting a power voltage when the flag is set to the specific logic value; and

a detector for detecting whether or not the boosted power voltage exceeds a predetermined value; and

a memory controller for permitting or inhibiting data writing in the non-volatile memory based on a detection result of the detector.

8. A microcomputer containing a non-volatile memory capable of reading and writing data, comprising:

a flag set to a specific logic value when data are rewritten in the non-volatile memory;

a detector for detecting whether or not a power voltage exceeds a predetermined value when the flag is set to the specific logic value; and

a memory controller for permitting or inhibiting data writing in the non-volatile memory based on a detection result of the detector,

wherein after the flag is set to a specific logic value, the correctness of the flag setting is checked; and

wherein the memory controller permits or inhibits data writing in the non-volatile memory based on the check result.

9. A microcomputer according to claim 8, wherein

after the flag is set to the specified value, the correctness of the flag setting is checked when the detector detects that the power voltage exceeds a predetermined value.

10. A microcomputer according to claim 9, wherein

the non-volatile memory stores a plurality of program commands;

and

the microcomputer further comprises;

a CPU for performing the program commands;

wherein

the CPU performs a specific program command when the power voltage has exceeded a predetermined value and determines whether or not the flag setting is correct.

11. A microcomputer according to claim 10, wherein

the CPU has an address counter for specifying a read address in the non-volatile memory;

and

the address counter is set to an address of the specified program command when the output of the voltage booster has exceeded a predetermined value.

12. A microcomputer containing non-volatile memory capable of reading and writing data, comprising:

a CPU for performing program commands, the CPU having an address counter for sending an address instruction to the non-volatile memory;

a flag which is set to a first logic value by the CPU based on a program command;

a voltage booster for boosting a power voltage when the flag is set at the first logic value;

a detector for detecting the boosted voltage and outputting a second logic value when the detected voltage is lower than a predetermined level and a third logic value when the detected voltage is equal to or higher than the predetermined level;

a latch which is reset when the output of the detector is the second logic value and is released from being reset when the output of the detector is the third logic value; and

a memory controller for setting the non-volatile memory to a state wherein data can be written when the latch output is set to a logic value different from the logic value when the latch is reset,

wherein the CPU sets the address counter to a specific value based on the output of the detector when the flag is set to the first logic value, and

wherein the CPU determines whether or not the flag is set correctly by decoding a program command read out from the non-volatile memory when the address counter is set to the specific value.

13. A microcomputer according to claim 12, wherein during a period from when a power is supplied to when it is stabilized, when the flag is incorrectly set to the first logic value, the latch is reset if the detected boosted voltage is less than the predetermined level, thereby preventing erroneous writing to the non-volatile memory.