Three-dimensional complementary field effect transistor process and structures

• US 5,925,909 A
• Filed: 11/08/1995
• Issued: 07/20/1999
• Est. Priority Date: 08/01/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sun, Yu, Liu, Yowjuang W.
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/555,556
• Time in Patent Office: 1,350 Days
• Field of Search: 257/408, 257/344, 257/329, 257/330, 257/331, 257/332, 257/334, 257/369, 257/401
• US Class Current: 257/331
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: Y10S 148/05 Etch and refill

Abstract

A field effect transistor has a short gate and is fabricated by: doping the bottom surface of a depression to form a relatively lightly doped region in the bottom of the depression; forming the gate of the field effect transistor on the sidewall of the depression such that the gate is insulated from the sidewall by a thin insulating layer; and implanting dopants to form the drain region and the source region of the transistor using the gate to mask a part of the relatively lightly doped region. The part of the relatively lightly doped region which is masked by the gate during implanting of the source and drain regions constitutes a lightly doped drain region of the transistor. The drain of the transistor is formed into the bottom of the depression. The length of the gate is primarily determined by the depth and/or profile of the sidewall. The source-to-drain on-resistance of the transistor is low because the transistor does not have a lightly doped source region. The transistor has high quality gate oxide because the sidewall of the depression upon which the gate oxide is grown is substantially free of ion impact damage.

Claims

1. An inverter, comprising:

a semiconductor material having a depression; and

two P-channel transistors and two N-channel transistors, the gates of all the four transistors being formed on sidewalls of the depression, and the gates of all the four transistors being electrically coupled together.

2. An inverter, comprising:

a first P-channel transistor having a gate disposed on a first sidewall of a first depression;

a second P-channel transistor having a gate disposed on a second sidewall of the first depression, the first and second sidewalls of the first depression being opposing and parallel to one another;

a first N-channel transistor having a gate disposed on a first sidewall of a second depression;

a second N-channel transistor having a gate disposed on a second sidewall of the second depression, the first and second sidewalls of the second depression being opposing and parallel to one another, the gates of the first and second P-channel transistors being coupled to the gates of the first and second N-channel transistors.