Semiconductor apparatus having a conductive sidewall structure

• US 5,925,912 A
• Filed: 03/26/1996
• Issued: 07/20/1999
• Est. Priority Date: 03/27/1995
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Arai, Masatoshi, Nakabayashi, Takashi
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/622,108
• Time in Patent Office: 1,211 Days
• Field of Search: 257/368, 257/336, 257/344, 257/408, 257/640, 257/641
• US Class Current: 257/344
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

In an active area on a semiconductor substrate is formed a MOS transistor including a gate insulating film, gate electrode, an insulating film formed on the entire surface of the substrate, a conductive side wall formed on the side surfaces of the gate electrode with the insulating film interposed therebetween, low concentration source/drain regions and high concentration source/drain regions. The high concentration drain region and the conductive side wall are electrically conducting to each other via a second interconnection within a second contact hole. In the usage of the MOS transistor, the conductive side wall is at the same potential as the drain voltage, thereby suppressing the degradation due to a hot carrier. In addition, since there is no need to provide an alignment margin between the second contact hole and the gate electrode, the area of the drain region is decreased. Thus, the invention provides a semiconductor apparatus which has a smaller active area and is suitable to refinement and a higher density, and a production method for the same.

Claims

1. A semiconductor apparatus comprising at least one n-type MOS transistor disposed on an active area surrounded by an isolation area formed on a semiconductor substrate, the n-type MOS transistor having a drain region and a source region, wherein a higher voltage is applied thereto the drain region than the source region, the n-type MOS transistor further including:

a gate insulating film formed in the active area surrounded by the isolation area on the semiconductor substrate;

a gate electrode formed on the gate insulating film, said gate electrode having side surfaces;

an insulating film formed so as to stretch over side surfaces of the gate electrode and the semiconductor substrate in the active area; and

a side wall made of a conductive material formed on each of the side surfaces of the gate electrode with the insulating film interposed therebetween, said sidewall being a continuous film surrounding said gate electrode;

wherein the source region and the drain region are formed on both sides of the gate electrode by introducing an impurity into the active area,

wherein the semiconductor apparatus is further provided with;

an interlayer insulating film formed on an area stretching over the gate electrode, the semiconductor substrate and the isolation area;

a first contact hole formed through the interlayer insulating film so as to reach the source region;

a second contact hole formed through the interlayer insulating film so as to reach the drain region and the conductive side wall; and

first and second contact members of a conductive material deposited within the first and second contact holes, respectively.

2. The semiconductor apparatus of claim 1, wherein the side wall has a thickness at its bottom of 150 nm or more.

3. The semiconductor apparatus of claim 1, further comprising a gate protection film formed on the gate electrode and made of an insulating material having high etching selectivity against the interlayer insulating film, said gate protection film being an etch stopper.

4. The semiconductor apparatus of claim 1, further comprising a gate protection film formed on the gate electrode and made of an insulating material;

and an entire protection film formed on the gate electrode, the active area and the isolation area, said protection film made of an insulating material having high etching selectivity against the isolation area and the gate protection film,

wherein the first and second contact holes are formed through the interlayer insulating film and the entire protection film.

5. The semiconductor apparatus of claim 4, wherein the isolation area and the gate protection film are made of a silicon oxide film, and the entire protection film is made of a silicon nitride film.